ASIC Design and STA Engineer

Clarus Advisers; Hyderabad; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Clarus Advisers is seeking an ASIC STA Engineer to join our Silicon engineering team in Hyderabad, India. You will own full-chip/ chiplet timing convergence, participate in floor planning and clock planning, and optimize CAD signoff flows while aligning with PD, RTL, and DFT teams.

The role requires hands-on experience with STA tools, ECO timing, and timing convergence across ASIC/SoC blocks, including sub-micron nodes.

Qualifications

• Hands-on experience in full-chip/sub-chip STA and timing convergence.
• Proficient in ECO timing fixes including crosstalk and noise analysis.
• Experience with CAD signoff flows and timing-driven optimization.

Responsibilities

• Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.
• Take part in top level floor plan and clock planning.
• Optimize, together with CAD signoff flows and methodologies.
• Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence.
• Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.

Skills

STA convergence

ECO timing fixes

Physical design timing

STA tools

Deep sub-micron timing

Domain-specific STA

Synthesis & EC

DFT timing closure

AMS timing closure

Automation flows

Job description

Company Overview

Our client is a Research lead organisation focusing on cutting-edge software, AI, and hardware innovation.

Position Overview

ASIC STA Engineer to join our outstanding Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms.

Responsibilities

• Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.
• Take part in top level floor plan and clock planning.
• Optimize, together with CAD signoff flows and methodologies.
• Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence.
• Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.

Skills & Experience

• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
• Expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis.
• Experience in physical design and optimization e.g., synthesis, placement, routing, logic restructuring, etc. to improve timing and power.
• Expertise and in-depth knowledge of industry standard STA and timing convergence tools.
• Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.
• Background in domain specific STA and timing convergence, such as GPUs, CPUs, LPU or SOCs
• Background in logic synthesis and equivalence checking/FV.
• Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc.
• Understanding and timing closure of digital logic/macros in AMS designs/IPs.
• Experience in methodology and/or flow development as well as automation.