Lead STA Engineer

Broadcom; Pune District; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Broadcom in Pune, India seeks an experienced STA Engineer to lead timing closure for block and full-chip designs, ensuring robust signoff readiness across modes and corners. You will own timing constraint development and collaborate with Synthesis, CTS, Physical Design, and Design teams to drive ECO-based optimizations through tape out.

The role requires hands-on expertise in setup/hold, derates, OCV/AOCV/POCV, and advanced timing concepts, with proficiency in SDC, false paths, and multicycle

Qualifications

• 15+ years of experience in STA and timing closure for block and/or full-chip designs.
• Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.
• Hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
• Good understanding of clock tree, clock uncertainty, latency, skew, and jitter.
• Expertise in timing constraints development and debugging.
• Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
• Experience with timing closure techniques and ECO methodologies.
• Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Good scripting skills in Tcl, Perl, or Python. Exposure to automation and flow development.
• Ability to analyze and resolve timing violations independently.
• Experience in low-power timing analysis and UPF/CPF-aware STA.
• Expertise with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure.
• Good knowledge of advanced technology nodes and variation-aware signoff methodologies.
• Experience in collaborating cross-functionally with PD, RTL, and Signoff teams.

Responsibilities

• Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
• Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
• Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
• Drive timing closure through ECO implementation and timing optimization.
• Analyze timing impact due to process, voltage, and temperature variations.
• Support timing signoff for pre-layout and post-layout stages.
• Perform cross-functional reviews for timing convergence and provide recommendations.
• Generate timing reports and communicate closure status to project stakeholders.

Skills

STA expertise

Timing closure

Scripting (Tcl/Python)

Cross-functional collaboration

Independent problem solving

Tools

Synopsys PrimeTime

Cadence Tempus

Tcl/Python scripting

Job description

Job Description:

In this role, the Engineer will apply and lead Broadcom's proven design methodology and milestone flow to meet rigorous criteria for achieving Right-First-Time silicon. The STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tape out.

Responsibilities include, but are not limited to:

• Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
• Work closely with Physical Design, Synthesis, CTS, and Design teams to achieve timing closure.
• Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
• Drive timing closure through ECO implementation and timing optimization.
• Analyze timing impact due to process, voltage, and temperature variations.
• Support timing signoff for pre-layout and post-layout stages.
• Perform cross-functional reviews for timing convergence and provide recommendations.
• Generate timing reports and communicate closure status to project stakeholders.

Minimum Qualifications:

• 15+ years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs.
• Strong understanding of CMOS fundamentals, timing concepts, and semiconductor design flow.
• Hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
• Good understanding of clock tree, clock uncertainty, latency, skew, and jitter.
• Expertise in timing constraints development and debugging.
• Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
• Experience with timing closure techniques and ECO methodologies.
• Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Good scripting skills in Tcl, Perl, or Python. Exposure to automation and flow development.
• Ability to analyze and resolve timing violations independently.
• Experience in low-power timing analysis and UPF/CPF-aware STA.
• Expertise with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure.
• Good knowledge of advanced technology nodes and variation-aware signoff methodologies.
• Experience in collaborating cross-functionally with PD, RTL, and Signoff teams.

R027491