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ACL Digital in Bengaluru is seeking a skilled and motivated STA Engineer to join their backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks, focusing on performance, power, and area optimization.
The ideal candidate should have over 4 years of experience and knowledge in constraint creation and maintenance as well as DFT modes in STA timing closure.
We are looking for a skilled and motivated STA Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure.