Memory Circuit Design Engineer

LeadSOC Technologies Pvt Ltd; Bengaluru; Sur place; INR 4 500 000 - 7 500 000; Plein temps

Résumé du poste

LeadSOC Technologies Pvt Ltd in Bengaluru seeks an experienced Memory Circuit Design Engineer to drive transistor-level SRAM memory design for advanced semiconductor nodes. The role focuses on designing SRAM bitcells, sense amplifiers, and peripheral circuitry, with PPA optimization across process nodes.

The candidate will perform rigorous circuit simulations, timing/power analyses, and post-layout verification while collaborating with memory architecture, physical design, and silicon validation

Qualifications

• B.E./B.Tech in Electrical/Electronics or related field.
• Strong experience in SRAM/memory circuit design and transistor-level layout.
• Proficiency with Cadence Virtuoso and SPICE-based simulators; familiarity with PVT analysis.

Responsabilités

• Design and develop SRAM bitcells, sense amplifiers, write drivers, decoders, and peripheral circuits.
• Perform transistor-level schematic design, circuit simulation, and optimization for power, performance, and area (PPA).
• Conduct pre-layout and post-layout simulations, including timing, noise, stability, and power analysis.
• Perform PVT corner analysis, Monte Carlo simulations, mismatch analysis, and circuit characterization.
• Collaborate with memory architecture, custom layout, physical design, and silicon validation teams.
• Support parasitic extraction, layout verification, design robustness, and yield optimization.
• Debug circuit-level issues and support silicon bring-up, characterization, and failure analysis.
• Evaluate advanced process nodes and implement innovative circuit techniques for memory performance and power efficiency.

Connaissances

SRAM design

Memory circuit design

VLSI CAD tools

Cadence Virtuoso

SPICE simulation

PVT analysis

Post-layout verification

Power/Performance/Area optimization

Formation

B.E./B.Tech in Electrical/Electronics

Outils

Spectre

HSPICE

Parasitic extraction tools

Description du poste

We are looking for an experienced Memory Circuit Design Engineer with strong expertise in transistor-level circuit design, SRAM design, and custom memory development for advanced semiconductor technologies. The ideal candidate will drive circuit design, simulation, characterization, and PPA optimization for high-performance, low-power SoCs.

Key Responsibilities

• Design and develop SRAM bitcells, sense amplifiers, write drivers, decoders, and memory peripheral circuits.
• Perform transistor-level schematic design, circuit simulation, and optimization for power, performance, and area (PPA).
• Conduct pre-layout and post-layout simulations, including timing, noise, stability, and power analysis.
• Perform PVT corner analysis, Monte Carlo simulations, mismatch analysis, and circuit characterization.
• Collaborate with memory architecture, custom layout, physical design, and silicon validation teams.
• Support parasitic extraction, layout verification, design robustness, and yield optimization.
• Debug circuit-level issues and support silicon bring-up, characterization, and failure analysis.
• Evaluate advanced process nodes and implement innovative circuit techniques for memory performance and power efficiency.

Required Technical Skills

• 10–16 years of hands-on experience in VLSI custom circuit design, with strong exposure to memory circuit design.
• Expertise in SRAM design, memory bitcells, sense amplifiers, and peripheral circuitry.
• Strong understanding of CMOS fundamentals, transistor-level design, device physics, and circuit behavior.
• Proficiency in Cadence Virtuoso and SPICE-based simulation tools such as Spectre or HSPICE.
• Experience in PVT analysis, Monte Carlo simulations, mismatch analysis, and circuit characterization.
• Knowledge of timing optimization, low-power design, signal integrity, and process variation.
• Experience with custom layout collaboration, parasitic extraction, and post-layout verification.
• Understanding of advanced semiconductor process technologies and memory design constraints.

Preferred Qualifications

• Experience in embedded SRAM, register files, and high-performance SoC memory subsystems.
• B.E./B.Tech/M.E./M.Tech in Electrical Engineering, Electronics, VLSI Design, or a related discipline.
• Exposure to memory compilers, memory characterization, and silicon validation.
• Knowledge of yield improvement, statistical circuit analysis, and advanced-node design challenges.
• Strong analytical, problem-solving, and cross-functional collaboration skills.