Lead Product Engineer - Design Verification (MM/VIP)

Cadence; Ahmedabad District; On-site; INR 1,500,000 - 2,500,000; Full time

Benefits offered by this job

Creative and innovative work environment

Employee-friendly policies

Collaboration-focused culture

Job summary

A leading technology firm is seeking a Lead Product Engineer to drive the development of products and technologies in Ahmedabad. This role involves significant responsibility for product success within the Memory domain of Verification IP. Candidates must possess strong verification expertise, along with experience in developing Verification environments using System Verilog. Ensure to collaborate effectively across teams and manage client technical needs. This role requires about 20% travel and cross-site collaboration worldwide.

Qualifications

• 4-8 years of experience with Design and Verification.
• Experience with developing Verification environments using System Verilog.
• Working knowledge of Memory protocols.

Responsibilities

• Lead projects with high resource, risk, and complexity.
• Manage issue resolution with vendors on tech/product quality.
• Communicate complex ideas to persuade others.

Skills

Verification expertise

System Verilog

UVM methodology

Problem-solving

Debugging skills

Education

BTech/BE/MTech/ME or equivalent

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Title: Lead Product Engineer

Location: Ahmedabad

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting‑edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee‑friendly policies focus on the physical and mental well‑being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Summary

Drives development of products and technologies and has material responsibility for the success of that product/technology. MM VIP PE is expected to become an expert in the Memory domain of Verification IP family – protocol and product‑wise. The memory domain has many protocols such as SDRAM protocols (DDR5), SGRAM protocols (GDDR6), Memory Controller and PHY protocols (DFI), and others. The Cadence VIP Portfolio includes Memory Models that enable advanced verification of these protocols. The PE’s main role is to help accelerate VIP Portfolio adoption at Cadence’s top tier customers by supporting pre‑sales technical activities. To ensure that, one must have strong verification expertise and understand customer design and verification flows. As a MM VIP and protocol expert, PE drives product knowledge transfer across our field engineers and customers, providing training and developing collaterals. The PE will also need to translate high‑level requirements from customers into a technical spec and drive the product definition that fits the customer needs. The PE is expected to work independently and collaborate with other team members (R&D, Marketing, Customer Support, Field Teams) to ensure all dimensions of the product are aligned. This role requires approximately 20% travel and cross‑site collaboration over multiple geographies (Asia Pacific, Europe, US‑East, US‑South and US‑West).

Job Responsibilities

• Leads projects with high resource, risk and/or complexity
• Develops and leads large and multiple cross‑functional and cross‑organizational programs, initiatives, and activities with high resource requirements, risk and/or complexity
• Continually evaluates technology effectiveness/data interoperability of complex systems
• Manages issue resolution with vendors on tech/product quality and functionality and influences vendor roadmap and direction of products
• Communicates highly complex ideas, anticipates potential objections and persuades others, often at senior levels, to adopt a different point of view.

Experience And Technical Skills Required

• At least 4 – 8 years of experience with Design and Verification
• Experience with Developing Verification environments using System Verilog
• Working knowledge and experience with the UVM methodology
• Good experience on solving complex problems where analysis of situations or data requires an in‑depth evaluation of various factors.
• Exercises judgment within broadly defined practices and policies in selecting methods, techniques, and evaluation criteria for obtaining results.
• Excellent problem‑solving and debugging skills
• Familiarity with Memory protocols is a must.
• Knowledge of the DFI protocol is a plus.

Qualifications

• BTech/BE/MTech/ME or equivalent with Electrical, Electronics & Comm or Computer Science Engineering

Behavioral Skills Required

• Must possess strong written, verbal and presentation skills
• Ability to establish a close working relationship with both customer peers and management
• Explore what’s possible to get the job done, including creative use of unconventional solutions
• Work effectively across functions and geographies
• Push to raise the bar while always operating with integrity

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