Sr Principal Design Engineer

Cadence; Bengaluru; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

Cadence is looking for an experienced professional in the VLSI domain. The ideal candidate should have 12-14 years of experience and a Master’s or Bachelor’s degree in engineering. Strong expertise in Verilog and HVL with UVM/OVM methodology is essential.

This role involves independent project management and proficiency in Perl/Tcl scripting. Join us in making significant technological impacts.

Qualifications

• 12-14 years of work experience in the VLSI domain.
• Strong RTL and GLS simulation debug skills.
• Ability to manage project schedule and delivery independently.

Skills

Verilog

HVL (SV, Specman e)

UVM/OVM/eRM methodology

Assertions development

Functional and code coverages

Test-bench development

Perl/Tcl scripting

Education

Master’s or Bachelor’s degree in engineering

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• 12-14 years of work experience in the VLSI domain with a Master’s or Bachelor’s degree in engineering.
• Strong expertise in Verilog, HVL (SV, Specman e) with UVM/OVM/eRM methodology.
• Expertise in assertions development/closure, constraint randomization, functional and code coverages, and formal verification.
• Expertise in test-bench development.
• Strong RTL and GLS (with or without SDF) simulation debug skills.
• Ability to manage project schedule and delivery independently.
• Proficiency in Perl/Tcl scripting and automation.

We’re doing work that matters. Help us solve what others can’t.