Sr Principal Design Engineer

Cadence; Ahmedabad District; On-site; INR 600,000 - 1,200,000; Full time

Job summary

A leading technology firm is seeking an experienced RTL Design Engineer to join their DDR Memory Controller IP development team in India. The role focuses on RTL design and support, ensuring compliance with design guidelines and verification regressions. Candidates must possess a BE/B.Tech/ME/M.Tech in Electrical, Electronics, or VLSI, along with expertise in Verilog and System Verilog. This is an opportunity to make a significant impact in a technology-driven environment.

Qualifications

• Experience as a design and verification engineer with RTL design and development.
• Experience in RTL design using Verilog.
• Experience with System Verilog and UVM based environment.

Responsibilities

• Design and support the RTL of the DDR Memory Controller solution.
• Ensure various customer configurations are clean as part of verification regressions.
• Support customers and ensure design is clean for LINT and CDC design guidelines.

Skills

RTL Design using Verilog

System Verilog

UVM based environment usage

AXI3/4

DDR Memory controller experience

Education

BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description

• RTL Design Engineer for DDR Memory Controller IP development team.
• The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
• The work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines.

Position Requirements

• BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
• RTL Design using Verilog is a must.
• System Verilog experience and experience with UVM based environment usage / debugging is required.
• AXI3/4 experience is desired.
• DDR Memory controller and protocol experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.
• Prior experience in IP development teams would be an added advantage.

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