Lead PrincipalRTL Design Engineer

Cadence; Pune District; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Cadence is seeking a Principal Senior Principal Lead Design Engineer for SoC/Subsystem/IP Design in Pune. You will own end-to-end RTL design, translate architecture into micro-architecture, and drive high-quality, reusable implementations that meet power, performance, and area targets.

Five to sixteen years of digital design experience with strong Verilog/SystemVerilog, AMBA protocols, and cross-functional collaboration with verification, physical design, DFT, firmware, and architecture teams

Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
• 10 to 16 years of experience in digital design with IP/SoC development.
• Strong knowledge of AMBA protocols (AXI, AHB, and APB) and RTL/verification flow.

Responsibilities

• Own end-to-end RTL design and development of SoC, subsystem, and IP blocks.
• Translate architecture and product requirements into micro-architecture and implementation plans.
• Develop RTL in Verilog/SystemVerilog with emphasis on correctness and reusability.
• Lead design of key blocks: interconnects, controllers, bridges, memory interfaces, datapaths, control logic.
• Drive design integration and resolve timing, interface, and functionality issues.
• Mentor junior engineers and contribute to reusable IP and tooling improvements.

Skills

Digital design fundamentals

Micro-architecture

Verilog/SystemVerilog

AMBA (AXI/AHB/APB)

Debugging & synthesis

Scripting (Python/Perl/Tcl/Shell)

Cross-functional collaboration

Excellent communication

Education

Bachelor's or Master's in Electronics/Electrical/Computer Engineering

Job description

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.

About the Role

Principal Senior Principal Lead Design Engineer, SoC / Subsystem / IP Design

Experience

5 to 16 years

Role Summary

Lead the design and integration of complex SoC, subsystem, and IP blocks from architecture interpretation through RTL delivery and design closure. Own micro-architecture, RTL development, quality reviews, and cross-functional coordination with verification, physical design, DFT, firmware, and architecture teams. Drive high-quality, reusable, and implementation-ready designs aligned to power, performance, and area targets.

Responsibilities

• Own end-to-end RTL design and development of SoC, subsystem, and IP blocks.
• Translate architecture and product requirements into detailed micro-architecture and implementation plans.
• Develop high-quality RTL in Verilog/SystemVerilog with focus on correctness, reusability, and scalability.
• Lead design of key blocks such as interconnects, controllers, bridges, memory interfaces, datapaths, and control logic.
• Drive block-level and subsystem-level design integration and resolve interface, timing, and functionality issues.
• Work closely with verification teams to review test plans, support debug, and ensure design quality and closure.
• Collaborate with physical design teams on timing, power, area, clocking, reset, and synthesis constraints.
• Support DFT, CDC, RDC, lint, low-power, and formal checks, and drive closure on design issues.
• Review specifications, micro-architecture documents, RTL, and design changes to ensure robustness and quality.
• Analyze and resolve design bugs found in simulation, emulation, silicon bring-up, or customer use cases.
• Mentor junior engineers and provide technical direction on coding practices, design quality, and methodology.
• Contribute to design methodology improvements, reusable IP development, and automation initiatives.

Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
• 10 to 16years of experience in digital design with strong exposure to IP, subsystem, and SoC development.

Required Skills

• Solid understanding of digital design fundamentals, FSMs, pipelines, arbitration, buffering, and clock/reset design.
• Strong experience in micro-architecture definition and hardware implementation.
• Good understanding of AMBA protocols such as AXI, AHB, and APB.
• Experience in designing interconnects, bus fabrics, DMA, memory-mapped peripherals, control/data path logic, or protocol bridges.
• Strong debugging skills for simulation, synthesis, and integration issues.
• Familiarity with lint, CDC, RDC, synthesis, STA constraints, DFT, and low-power design flows.
• Exposure to power, performance, and area optimization techniques.
• Scripting experience in Python, Perl, Tcl, or Shell for automation and productivity improvements.
• Strong communication and cross-functional collaboration skills.

Preferred Skills

• Experience with PCIe, DDR, NoC, cache/coherency, security, or safety-related designs.
• Exposure to low-power design methodologies including UPF/CPF.
• Experience with formal verification support and silicon debug.
• Experience leading small design teams or owning major subsystems in large SoC programs.