Sr Principal Design Engineer

Cadence; Ahmedabad District; On-site; INR 900,000 - 1,400,000; Full time

Job summary

Cadence, a global leader in software, hardware and IP for the electronics industry, invites talented RTL Design Engineers to join the DDR Memory Controller IP team in Ahmedabad. You will design and support RTL, add new features, verify across configurations and help customers through debug and optimization tasks.

The role emphasizes Verilog/SystemVerilog, UVM-based verification, lint and CDC guidelines, and experience with DDR4/LPDDR4 protocols. Prior IP development experience is a plus.

Qualifications

• BE/B.Tech/ME/M.Tech in Electrical/Electronics/VLSI with RTL design experience.
• RTL design using Verilog is a must.
• SystemVerilog experience with UVM-based verification and debugging is required.
• AXI3/4 experience is desired.
• DDR memory controller protocol experience is highly desirable; IP development experience is a plus.

Responsibilities

• Design and support RTL for the DDR Memory Controller IP.
• Add new features to RTL and ensure configurations pass verification regressions.
• Support customers and provide debugging assistance.
• Ensure RTL design follows lint and CDC guidelines.

Skills

RTL Design

Verilog

SystemVerilog

UVM

AXI3/4

DDR Memory Controller

Education

BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI

Tools

UVM

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Position Description

• RTL Design Engineer for DDR Memory Controller IP development team.
• The role would include the design and support of the RTL of the DDR Memory Controller solution of Cadence. All leading DDR memory protocols will be supported – including DDR4/LPDDR4.
• The work involved will be working with the existing RTL, the addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring the design is clean for LINT and CDC design guidelines.

Position Requirements

• BE/B.Tech/ME/M.Tech - Electrical / Electronics / VLSI with experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
• RTL Design using Verilog is a must.
• System Verilog experience and experience with UVM based environment usage / debugging is required.
• AXI3/4 experience is desired.
• DDR Memory controller and protocol experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.
• Prior experience in IP development teams would be an added advantage.

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