Principal Design Engineer

Cadence; Hyderabad; On-site; INR 6,000,000 - 9,000,000; Full time

Job summary

Cadence in Hyderabad invites a Principal Engineer to architect and deliver high-speed Analog/Mixed-Signal IPs for cutting-edge interfaces like UCIe, PCIe, DDR/LPDDR and HBM.

You will lead cross-functional teams across Analog, Layout, AMS Verification, Digital and Physical Design, mentor engineers, and drive execution, with opportunities to manage project staffing and customer engagements in a global setting.

Qualifications

• Experience designing high-speed interface IPs from architecture to silicon.
• Strong fundamentals in analog design, I/O and signal integrity.
• Proven track record leading large technical teams and delivering IPs.

Responsibilities

• Architect, design, and deliver high-speed Analog/Mixed-Signal IPs and subsystems.
• Drive design closure for TX/RX, PLL, DLL, CDR, Clocking, Datapath, I/O and interfaces.
• Lead IP programs with cross-functional teams across Analog, Layout, AMS Verification, Digital and Physical Design.
• Mentor engineers and drive technical excellence, innovation and execution.
• For management roles, lead project staffing, risk management and customer engagements.

Skills

UCIe IP

PCIe Gen3-6

HBM/Memory Interfaces

SerDes design

Analog/Mixed-Signal

Leadership & mentoring

Education

BE/BTech/ME/MTech/MS

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Job Opening: Analog Circuit DesignRoles: Principal EngineerExperience: 10–17+ YearsLocation: Hyderabad (Preferred) / Noida / PuneEducation: BE / B.Tech / ME / M.Tech / MSJoin a team building next-generation UCIe, D2D, PCIe, DDR/LPDDR, HBM, GDDR, and SerDes IPs on advanced technology nodes.Key Responsibilities

• Architect, design, and deliver high-speed Analog/Mixed-Signal IPs and subsystems.
• Drive design closure for TX/RX, PLL, DLL, CDR, Clocking, Datapath, I/O, and interface circuits.
• Lead complex IP programs involving cross-functional teams including Analog Design, Layout, AMS Verification, Digital, and Physical Design.
• Mentor engineers and drive technical excellence, innovation, and execution.
• For management roles, lead project execution, staffing, risk management, and customer engagements.

Required Skills

• Strong expertise in high-speed interface design:
  • UCIe / Die-to-Die (D2D)
  • PCIe Gen3/4/5/6
  • DDRx / LPDDRx / GDDRx / HBM
  • High-speed SerDes architectures
• Strong Analog Design and I/O fundamentals.
• Knowledge of SI/PI, ESD, Reliability, Jitter, Timing, and PPA optimization.
• Experience delivering complex IPs from architecture to silicon.
• Excellent communication, leadership, and problem-solving skills.

Preferred Qualifications

• Experience with advanced technology nodes (16nm, 12nm, 10nm, 7nm, 5nm, 3nm).
• Experience in IP architecture, technology migration, and design reuse methodologies.
• Proven track record of leading large technical teams and delivering high-performance connectivity or memory interface solutions.

Ideal candidates bring deep technical expertise, strong execution skills, and the ability to lead the development of industry-leading high-speed interface IPs for AI, HPC, Networking, and Data Center applications.We’re doing work that matters. Help us solve what others can’t.