SR Engineer, ASIC DFT

1840 Micron Tech. OP India LLP; Hyderabad; Hybrid; INR 1,500,000 - 2,500,000; Full time

Benefits offered by this job

PTO

Medical benefits

Job summary

1840 Micron Tech. OP India LLP is seeking engineers to implement innovative DFT techniques at RTL and Gate level for SOCs. The role involves generating and validating ATPG patterns, collaborating with multi-functional teams, and contributing to DFT methodology development.

The ideal candidate holds a Bachelor’s or Master’s Degree in relevant fields and has 5+ years of experience in DFT. Proficiency in programming languages like Verilog and Python is essential, along with experience in industry-standard tools.

Benefits include PTO and medical benefits.

Qualifications

• 5+ years of industry experience with DFT of sophisticated SOCs.
• Core skills in scan and memory diagnosis.
• Proficiency in multiple programming languages.

Responsibilities

• Accountable for innovative DFT implementation.
• Generate and validate ATPG patterns.
• Validate the DFT implementation using RTL and Gate level simulation.

Skills

Scan Codec insertion

Memory BIST and Repair implementation

Logic BIST

ATPG

BSCAN & JTAG

Verilog

VHDL

C/C++

TCL

Perl

Python

Education

Bachelor’s or Master’s Degree in Electronics Engineering, Microelectronics, Software Engineering

Tools

Siemens tools

Synopsys tools

Cadence tools

Job description

Responsibilities

• Accountable for innovative DFT implementation (Scan, MBIST, LBIST & Boundary Scan) at RTL and Gate level for a given SOC at hard macro and chip top level.
• Generate and validate ATPG patterns using simulations.
• Validate the DFT implementation using RTL and Gate level simulation.
• Work with multi‑functional teams on STA, synthesis, LEC, CLP, verification and validation.
• Support silicon bring‑up activities to guarantee the highest stability of test patterns/program.
• Contribute to the overall DFT methodology development.

Required Qualifications

• Bachelor’s or Master’s Degree (or equivalent experience) in Electronics Engineering, Microelectronics, Software Engineering or a related field.
• 5+ years of industry experience with DFT of sophisticated SOCs.
• Core skills: Scan Codec insertion, Memory BIST and Repair implementation, Logic BIST, ATPG, BSCAN & JTAG (IEEE 1149.1 & IEEE 1687), fault simulation, ATPG fault models (SAF, TDF, SDD, PDT, etc.), SDF‑annotated gate‑level verification, scan and memory diagnosis.
• Experience with Siemens, Synopsys and/or Cadence Cadence tools.
• Proficiency in Verilog, VHDL, C/C++, TCL, Perl and/or Python coding.

Nice to Have

• Knowledge of IEEE 1149.6, 1500 and 1838.
• Experience with hierarchical scan implementations and core‑wrapping concepts.
• Handling multi‑clock domains and low‑power design implementation.
• Experience with SSN, 2.5D or 3D IC DFT implementation.
• Effective communication with multi‑functional teams across geographies and time zones.
• Strong time‑management and multi‑tasking skills.

Job Location

Hyderabad or Bangalore

Benefits

• PTO
• Medical benefits

Equal Opportunity

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.