SR Engineer, ASIC DFT

Micron Technology, Inc; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Micron Technology, Inc is seeking a Senior ASIC DFT Engineer in Hyderabad or Bangalore, India. The role involves implementing DFT solutions for memory controller and SOC IPs, requiring expertise in DFT methodology and strong coding skills.

The ideal candidate will have at least 5 years of industry experience, a relevant degree, and proficiency in tools like Siemens and Synopsys. Relocation assistance may be provided on a case-by-case basis.

Qualifications

• 5+ years of industry experience in DFT for sophisticated SOCs.
• Proficient in scan codec insertion, memory BIST and repair.
• Experience with hierarchical scan implementations.

Responsibilities

• Design and implement DFT at RTL and gate level.
• Generate and validate ATPG patterns using simulation.
• Collaborate with multi-functional teams on verification processes.

Skills

DFT at RTL and gate level

ATPG patterns generation

Verilog, VHDL, C/C++, TCL, Perl, Python

Siemens, Synopsys and/or Cadence CAD tools

Strong communication skills

Education

Bachelor’s or Master’s degree in Electronics Engineering or related field

Tools

DFT methodology

Scan codec

Memory BIST

Logic BIST

Job description

Senior ASIC DFT Engineer

Micron Technology is looking for a Senior ASIC DFT Engineer to implement design‑for‑test (DFT) solutions for memory controller and SOC IPs.

Responsibilities

• Design and implement DFT at RTL and gate level, including scan, MBIST, LBIST, and boundary‑scan.
• Generate and validate ATPG patterns using simulation.
• Validate DFT implementation with RTL and gate level simulation.
• Collaborate with RTL, DV, physical implementation, test engineering, and product engineering teams on STA, synthesis, logic‑level extraction, clock‑tree planning, and verification.
• Support silicon bring‑up activities to ensure test pattern stability.
• Contribute to overall DFT methodology development.

Qualifications

• Bachelor’s or Master’s degree in Electronics Engineering, Microelectronics, Software Engineering or related field, or equivalent experience.
• 5+ years of industry experience in DFT for sophisticated SOCs.
• Proficient in scan codec insertion, memory BIST and repair, logic BIST, ATPG, BSCAN & JTAG (IEEE1149.1, IEEE1687), fault simulation, SDF‑annotated gate‑level verification, scan and memory diagnosis.
• Experience with Siemens, Synopsys and/or Cadence CAD tools.
• Strong coding skills in Verilog, VHDL, C/C++, TCL, Perl and/or Python.

Nice to Have

• Knowledge of IEEE1149.6, IEEE1500, IEEE1838.
• Experience with hierarchical scan implementations and core wrapping concepts.
• Handling of multiprocess‑domain and low‑power design implementation.
• Experience with SSN, 2.5D or 3D IC DFT implementation.
• Strong communication skills across multi‑functional teams and time zones.
• Excellent time management and multi‑tasking ability.

Location

Hyderabad or Bangalore, India. Relocation assistance may be provided on a case‑by‑case basis.

Equal Opportunity Employment

Micron is an equal‑opportunity workplace. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.