Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)

Micron Technology; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Micron Technology in Hyderabad, India is seeking a Senior Engineer for their Advanced Packaging Build Enablement Engineering team. The role involves developing strategies for High Bandwidth Memory (HBM) packaging programs, with responsibilities including die design, tapeout processes, and collaboration with multiple teams. Applicants should have a Master’s or PhD in Electrical Engineering and possess significant industry experience, particularly with advanced packaging techniques.

Qualifications

• 5+ years in die design and physical layout engineering.
• Hands-on experience with HBM and advanced packaging programs.
• Experience with TSV-based die design.

Responsibilities

• Build and tapeout PWF Reticles Design.
• Develop DFTs in packaging test vehicles.
• Coordinate with various teams for test structures.

Skills

Physical design expertise

Experience with EDA tools

Knowledge of DRC/LVS/ERC flows

Understanding of TSV design rules

Working knowledge of DFT structures

Education

Master’s or PhD in Electrical Engineering

Tools

Cadence Virtuoso

Innovus

Mentor Calibre

Synopsys IC Compiler

Job description

About the Role

We are seeking an exceptionally skilled and ambitious Senior Engineer for our Advanced Packaging Build Enablement Engineering (APDEE) team, located in Hyderabad, Telangana, India. This role is pivotal in accomplishing a flawless build strategy for High Bandwidth Memory (HBM) packaging programs.

Key Responsibilities

• Build and tapeout PWF Reticles Design
• Develop DFTs in test vehicles for packaging related fail modes
• Coordinate with HIG-HBM DTPCO and HIG-HBM teams to build test structures for live die
• Design rules management, process design rules for PWF, wafer thinning and dicing, die stacking etc.
• BEOL Design – mainly engagement with FE Integration teams
• Engage with Scribe Design team to capture Advanced Packaging requirements and review
• TSV design engagement with HIG-HBM DTPCO teams (electrical, thermal and mechanical performance)
• Creation and maintenance of DFMEA related to advanced packaging process steps like PWF, die stacking etc.
• Perform electrical simulations to understand the fail mode mechanism

Required Qualifications

Education

• Master’s or PhD degree in Electrical Engineering, Computer Engineering, or related field

Experience

• 5+ years of experience in die design and physical layout engineering
• Direct hands‑on experience with HBM, 3D‑IC, or advanced packaging programs (CoWoS, SoIC, FOVEROS, or equivalent)
• Proven experience with TSV‑based die design including KOZ management, micro‑bump layout, and backside RDL

Technical Skills

• Deep expertise in physical design and layout using industry‑standard EDA tools (Cadence Virtuoso, Innovus, Mentor Calibre, Synopsys IC Compiler)
• Strong knowledge of DRC/LVS/ERC sign‑off flows and foundry PDK rule interpretation
• Solid understanding of TSV design rules, stress modeling implications, and 3D integration layout constraints
• Working knowledge of DFT structures relevant to advanced packaging: daisy chains, BIST, boundary scan, IEEE P1838
• Familiarity with JEDEC HBM specifications (HBM2E, HBM3, HBM3E)
• Understanding of power integrity, signal integrity, and thermal considerations at the die‑package interface
• Experience with parasitic extraction and layout‑driven optimization for high‑speed memory interfaces

Preferred Qualifications

• Experience with hybrid bonding or direct bond interconnect (DBI) die design constraints
• Familiarity with chiplet architecture and disaggregated die design for heterogeneous integration
• Knowledge of HBM assembly (TCB, underfill, wafer thinning)
• Experience with layout automation scripting (Skill, Python, Tcl) for template generation and DRC waiver management
• Exposure to reliability physics relevant to advanced packaging: electromigration, stress‑voiding, thermo‑mechanical degradation
• Published work or patents in advanced packaging, 3D‑IC design, or memory interface design

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.