Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

1840 Micron Tech. OP India LLP is seeking a Sr Engineer for Advanced Packaging Build Enablement in Hyderabad, Telangana, India. This pivotal role focuses on the seamless integration of silicon design with advanced packaging for High Bandwidth Memory (HBM) programs.

The ideal candidate will possess a Masters or PhD in Electrical Engineering and over 5 years of relevant experience. Responsibilities include key collaborations across design teams and engaging in back-end-of-line (BEOL) design.

Qualifications

• 5+ years of experience in die design and physical layout engineering.
• Direct hands-on experience with HBM, 3D-IC, or advanced packaging programs.
• Experience with TSV-based die design including KOZ management.

Responsibilities

• Build and tapeout PWF reticles design.
• Develop DFTs in test vehicles for packaging-related fail modes.
• Manage design rules, process design rules for PWF.

Skills

Deep expertise in physical design and layout using industry standard EDA tools

Strong knowledge of DRC/LVS/ERC sign-off flows

Solid understanding of TSV design rules

Experience with parasitic extraction

Education

Masters or PhD degree in Electrical Engineering, Computer Engineering, or related field

Tools

Cadence Virtuoso

Innovus

Mentor Calibre

Synopsys IC Compiler

Job description

Sr Engineer, Advanced Packaging Build Enablement Engineering (APDEE), Hyderabad, Telangana, India.

This role is pivotal in accomplishing a flawless build strategy for High Bandwidth Memory (HBM) packaging programs. The Sr Engineer will sit at the critical intersection of silicon design and advanced packaging, responsible for executing advanced packaging related design strategy that enables world‑class HBM product integration. Responsibilities include collaborating with Micron’s various design teams (HIG DTPCO, DRAM designers worldwide) and supporting Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize manufacturing functions and assure the best cost, quality, reliability, time‑to‑market, and customer satisfaction.

Key Responsibilities

• Build and tapeout PWF reticles design.
• Develop DFTs in test vehicles for packaging-related fail modes.
• Coordinate with HIG-HBM DTPCO and HIG-HBM teams to build test structures for live die.
• Manage design rules, process design rules for PWF, wafer thinning, dicing, die stacking, etc.
• Engage in BEOL design with FE Integration teams.
• Collaborate with Scribe Design team to capture advanced packaging requirements and review.
• TSV design engagement with HIG-HBM DTPCO teams (electrical, thermal and mechanical performance).
• Creation and maintenance of DFMEA related to advanced packaging process steps like PWF and die stacking.
• Perform electrical simulations to understand fail‑mode mechanisms.

Required Qualifications

• Education: Masters or PhD degree in Electrical Engineering, Computer Engineering, or related field.
• Experience: 5+ years of experience in die design and physical layout engineering; direct hands‑on experience with HBM, 3D‑IC, or advanced packaging programs (CoWoS, SoIC, FOVEROS, or equivalent); proven experience with TSV‑based die design including KOZ management, micro‑bump layout, and backside RDL.
• Technical Skills: Deep expertise in physical design and layout using industry‑standard EDA tools (Cadence Virtuoso, Innovus, Mentor Calibre, Synopsys IC Compiler); strong knowledge of DRC/LVS/ERC sign‑off flows and foundry PDK rule interpretation; solid understanding of TSV design rules, stress modeling implications, and 3D integration layout constraints; working knowledge of DFT structures relevant to advanced packaging (daisy chains, BIST, boundary scan, IEEE P1838); familiarity with JEDEC HBM specifications (HBM2E, HBM3, HBM3E); understanding of power integrity, signal integrity, and thermal considerations at the die‑package interface; experience with parasitic extraction and layout‑driven optimization for high‑speed memory interfaces.

Preferred Qualifications

• Experience with hybrid bonding or direct bond interconnect (DBI) die design constraints.
• Familiarity with chiplet architecture and disaggregated die design for heterogeneous integration.
• Knowledge of HBM assembly (TCB, underfill, wafer thinning).
• Experience with layout automation scripting (Skill, Python, Tcl) for template generation and DRC waiver management.
• Exposure to reliability physics relevant to advanced packaging: electromigration, stress voiding, thermo‑mechanical degradation.
• Published work or patents in advanced packaging, 3D‑IC design, or memory interface design.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.