Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)

Micron Technology, Inc; Hyderabad; On-site; INR 1,800,000 - 2,500,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid family leave

Robust paid time-off program

Job summary

Micron Technology, Inc is searching for a skilled Sr Engineer to join their Advanced Packaging Build Enablement Engineering team in Hyderabad, India. This pivotal role involves executing advanced packaging related design strategies that integrate High Bandwidth Memory (HBM) products.

The successful candidate will have over 5 years of experience in die design, strong knowledge of semiconductor packaging, and be adept at using industry-standard EDA tools. Micron offers competitive benefits designed to support professional growth and well-being.

Qualifications

• 5+ years of experience in die design and physical layout engineering.
• Direct hands‑on experience with HBM, 3D‑IC, or advanced packaging programs.
• Deep expertise in physical design and layout using industry-standard EDA tools.

Responsibilities

• Build and tapeout PWF Reticles Design.
• Develop DFTs in test vehicles for packaging related fail modes.
• Coordinate with teams to build test structures for live die.

Skills

Physical design expertise

Experience with TSV-based die design

Knowledge of DRC/LVS/ERC sign-off flows

Understanding of power integrity

Familiarity with JEDEC HBM specifications

Experience with layout automation scripting

Education

Masters or PhD in Electrical Engineering or Computer Engineering

Tools

Cadence Virtuoso

Innovus

Mentor Calibre

Synopsys IC Compiler

Job description

Req. ID: JR95830 Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE)

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Are you ready to be part of a world-class team driving innovation at the intersection of silicon development and advanced packaging? We are seeking an exceptionally skilled and ambitious Sr Engineer for our Advanced Packaging Build Enablement Engineering (APDEE) team, located in Hyderabad, Telangana, India. This role is pivotal in accomplishing a flawless build strategy for High Bandwidth Memory (HBM) packaging programs.

Advanced Packaging Technology Development org is seeking an experienced and technically strong semiconductor design senior engineer to support HBM packaging program. This role sits at the critical intersection of silicon design and advanced packaging, responsible for executing advanced packaging related design strategy that enables world‑class HBM product integration. In this position, you will collaborate with Micron’s various design teams HIG DTPCO, DRAM designers all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time‑to‑market, and customer satisfaction.

Key Responsibilities

• Build and tapeout PWF Reticles Design
• Developing DFTs in test vehicles for packaging related fail modes
• Coordinate with HIG-HBM DTPCO and HIG-HBM teams to build test structures for live die
• Design rules management, process design rules for PWF, wafer thinning and dicing, die stacking etc
• BEOL Design – mainly engagement with FE Integration teams
• Engage with Scribe Design team to capture advanced packaging requirements and review
• TSV design engagement with HIG-HBM DTPCO teams (electrical, thermal and mechanical performance)
• Creation and maintenance of DFMEA related to advanced packaging process steps like PWF, die stacking etc
• Perform electrical simulations to understand the fail‑mode mechanism

Required Qualifications

Education

• Masters or PhD degree in Electrical Engineering, Computer Engineering, or related field required

Experience

• 5+ years of experience in die design and physical layout engineering
• Direct hands‑on experience with HBM, 3D‑IC, or advanced packaging programs (CoWoS, SoIC, FOVEROS, or equivalent)
• Proven experience with TSV‑based die design including KOZ management, micro‑bump layout, and backside RDL

Technical Skills

• Deep expertise in physical design and layout using industry‑standard EDA tools (Cadence Virtuoso, Innovus, Mentor Calibre, Synopsys IC Compiler)
• Strong knowledge of DRC/LVS/ERC sign‑off flows and foundry PDK rule interpretation
• Solid understanding of TSV design rules, stress modeling implications, and 3D integration layout constraints
• Working knowledge of DFT structures relevant to advanced packaging: daisy chains, BIST, boundary scan, IEEE P1838
• Familiarity with JEDEC HBM specifications (HBM2E, HBM3, HBM3E)
• Understanding of power integrity, signal integrity, and thermal considerations at the die‑package interface
• Experience with parasitic extraction and layout‑driven optimization for high‑speed memory interfaces

Preferred Qualifications

• Experience with hybrid bonding or direct bond interconnect (DBI) die design constraints
• Familiarity with chiplet architecture and disaggregated die design for heterogeneous integration
• Knowledge of HBM assembly (TCB, underfill, wafer thinning)
• Experience with layout automation scripting (Skill, Python, Tcl) for template generation and DRC waiver management
• Exposure to reliability physics relevant to advanced packaging: electromigration, stress voiding, thermo‑mechanical degradation
• Published work or patents in advanced packaging, 3D‑IC design, or memory interface design

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays. For additional information regarding the benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.