Senior IC Packaging Engineer - 8 to 10 Years - HYD

MosChip®

Hyderabad

On-site

INR 4,000,000 - 6,000,000

Full time

14 days+

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Job summary

MosChip is seeking an experienced Senior IC Packaging Engineer to lead architecture and development of advanced IC packaging, MCM, and SiP solutions. You will drive technology strategy for FCBGA, 2.5D, and chiplet architectures, collaborating with design teams, OSATs, and customers from feasibility to volume production.

You will own packaging roadmaps, perform DFM/DFT/DFR optimizations, and mentor junior engineers while engaging in customer discussions and pre-sales activities.

Qualifications

Bachelor's/Master's degree in a relevant engineering field.
8–10+ years in semiconductor packaging for SoCs, ASICs, or memory.
Hands-on with FCBGA, SiP, MCM, and chiplet architectures.
Experience with high-speed interfaces like PCIe, CXL, UCIe, and LPDDR/HBM.
Ability to lead packaging programs from concept to production.
Proficiency with Cadence Allegro APD or equivalent tools.

Responsibilities

Lead architecture definition for advanced IC, MCM, and SiP packaging.
Own technology selection, roadmaps, and performance trade-offs.
Drive 2.5D/3D packaging, RDL, and substrate stack-ups.
Guide design, floor planning, and layout for high-speed interfaces.
Perform electrical, thermal, mechanical, and reliability analysis.
Collaborate with foundries, OSATs, and suppliers for qualifications.
Mentor junior engineers and contribute to capability growth.
Engage in pre-sales discussions and customer proposals related to packaging.

Skills

FCBGA

SiP

MCM

Chiplet architectures

UCIe ecosystems

High-speed interfaces

Packaging leadership

DFM/DFT/DFR basics

Education

BE/MTech in Electrical Engineering

Semiconductor Technology or related field

Tools

Cadence Allegro APD

HFSS

SIwave

Ansys Designer

Clarity

Icepak

CST

Job description

Company Overview

MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.

About The Role

MosChip is seeking a experienced Senior IC Packaging Engineer to provide technical leadership in the coordination for architecture, design, and development of advanced IC Packaging, Multi-Chip Module (MCM), and System-in-Package (SiP) solutions. This role is ideal for a hands-on packaging expert with deep domain knowledge in advanced semiconductor packaging technologies, chiplet integration, high-speed interfaces, and heterogeneous system design.

The successful candidate will drive package architecture and technology strategy across next-generation packaging platforms including FCBGA, 2.5D/RDL Fan-Out, Silicon Interposers, Chiplet-Based Architectures, and Heterogeneous Integration. The role requires close collaboration with design teams, foundries, OSATs, substrate vendors, and customers from feasibility assessment through volume production.

Key Responsibilities

Lead the architecture definition, and execution of advanced IC, MCM, and SiP packaging solutions for high-performance and high-density semiconductor products, based on cross functional coordination.

Own package technology selection, roadmap development, and architecture decisions to meet performance, power, cost, schedule, and scalability objectives.

Drive advanced packaging initiatives involving FCBGA, 2.5D packaging, RDL Fan-Out, Silicon Interposers, Embedded Die, and UCIe-based Chiplet Architectures.

Perform and guide package design, floor planning, and physical layout for high-speed interfaces including PCIe, CXL, UCIe, LPDDR5X, HBM, Ethernet, and multi-gigabit SerDes.

Define substrate stack-ups, bumping strategies, RDL architectures, power delivery networks, high-speed routing methodologies, and signal integrity best practices.

Lead package-level electrical, thermal, mechanical, and reliability analysis to achieve robust product performance and manufacturability.

Develop and implement Design-for-Manufacturing (DFM), Design-for-Test (DFT), Design-for-Reliability (DFR), and yield optimization strategies.

Collaborate with foundries, OSATs, substrate suppliers, assembly partners, and EDA vendors to drive technology qualification and manufacturing readiness.

Conduct package feasibility studies, technology evaluations, risk assessments, and cost-performance trade-off analyses.

Establish scalable packaging methodologies, design guidelines, and reusable flows across multiple projects and product families.

Mentor junior engineers and contribute to the growth of packaging capabilities within the organization.

Provide technical leadership in customer discussions, proposals, and pre-sales engagements related to advanced packaging solutions.

Required Qualifications

B.E./M.Tech in Electrical Engineering, Electronics Engineering, Semiconductor Technology, or related field.

8-10+ years of industry experience in semiconductor package design and development for SoCs, ASICs, FPGA, AI/ML, Networking, HPC, Storage, or Memory products.

Strong hands-on expertise in:

Flip-Chip BGA (FCBGA); System-in-Package (SiP); Multi-Chip Modules (MCM)

Advanced substrates; RDL and Fan-Out Packaging; Silicon Interposers,

CSP, WLCSP, QFN, LQFP

Chiplet-based architectures and UCIe ecosystems

Deep understanding of SI, PI, TI & Mechanical Analysis related DFM concepts to achieve reliable and high yield packages

Proven experience in substrate design, escape routing, power distribution, high-speed package design, and package validation.

Hands-on experience with Cadence Allegro Package Designer (APD) or equivalent advanced package design tools.

Ability to work independently and drive complex programs from concept through production in a fast-paced environment.

Preferred Qualifications

Experience with HFSS, SIwave, Ansys Designer, Clarity, Icepak, CST, or equivalent simulation tools.

Knowledge of advanced interfaces such as UCIe, PCIe Gen5/Gen6, CXL, DDR5/LPDDR5, HBM, Ethernet, and AI accelerator packaging.

Experience working directly with leading foundries, OSATs, substrate manufacturers, and assembly/test partners.

Familiarity with advanced packaging roadmaps including 3D IC, Hybrid Bonding, CoWoS, Foveros, InFO, and next-generation heterogeneous integration technologies shall be a plus.