Principal / Lead Physical Design

ACL Digital; Bengaluru; Presencial; INR 4.000.000 - 7.000.000; Jornada completa

Descripción de la vacante

ACL Digital in Bengaluru is seeking a Principal/Lead SOC Physical Design Specialist to own RTL-to-GDSII execution on 16nm, 7nm and 5nm nodes. You will drive floorplanning, power grids, CTS architecture and low-power strategies while steering complex tape-outs and MMMC timing closure.

With 14+ years in PD and a proven track record on advanced nodes, you will mentor engineers and lead fast-paced design teams to deliver robust silicon blocks. Immediate to 30-days join possible.

Formación

• 14+ years of hands-on, end-to-end Physical Design experience.
• Proven tape-out track record on advanced process nodes.
• Experience with industry-standard EDA tools for implementation and sign-off.
• Available to join immediately or within 30 days.

Responsabilidades

• Own RTL-to-GDSII execution for complex tape-outs.
• Drive floorplanning, power grid design, and CTS architecture.
• Manage multi-corner multi-mode timing closure and SI/EM/IR analysis.
• Provide technical leadership and mentorship to the PD team.

Conocimientos

End-to-end PD

Floorplanning

Timing Closure

Power Integrity

MMMC

Mentoring

RTL-to-GDSII

EDA Tools

Herramientas

EDA tools

IC Compiler

Primetime

Calibre

Descripción del empleo

Are you ready to lead mission-critical tape-outs on bleeding-edge silicon? ACL Digital is looking for a Principal / Lead SOC Physical Design Specialist to own complete RTL-to-GDSII execution on advanced sub-micron process nodes.

If you thrive on solving complex floorplanning challenges, closing timing under extreme MMMC constraints, and steering high-performing engineering teams, this role is built for you.

What You’ll Drive

• Advanced Node Ownership: Drive physical design from floorplan to sign-off across 16nm, 7nm, and 5nm technologies.
• Complex Implementation: Design robust power grids, structure CTS architecture, and execute low-power design strategies.
• Full Sign-off Closure: Own multi-corner multi-mode (MMMC) timing closure, Signal Integrity (SI), and static/dynamic EM/IR-drop analysis.
• Technical Leadership: Lead complex tape‑outs, resolve architectural bottlenecks, and mentor top-tier engineering talent.

What We’re Looking For

• 14+ years of hands‑on, end-to-end Physical Design experience.
• Proven track record of successful tape‑outs on advanced process nodes.
• Expertise in industry‑standard EDA tools for implementation and sign-off verification.
• Ability to join immediately or within 30 days.

Ready to Shape Next-Gen Silicon?