SoC DFT Technical Manager, Google Cloud

Google LLC; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

Google LLC is seeking a Share SoC DFT Technical Manager to shape DFT architecture for multi-core SoCs and lead RTL-to-post-silicon activities. You will drive hierarchical scan compression, MBIST for large memories, and integration with high-speed I/O and JTAG networks.

The role demands 10+ years in SoC DFT, management experience, and proficiency in Tcl/Python/Perl for automation. This position anchors Google’s TPU and AI/ML hardware strategy in a collaborative, global team.

Qualifications

• Bachelor's degree in Electrical, Computer Engineering or equivalent practical experience.
• 10 years of experience in SoC DFT architecture and design.
• 10 years of experience in DFT protocols including Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).
• 10 years of experience with industry-standard EDA tools such as Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus.
• 4 years of people management experience developing employees and leading multiple SoC projects from RTL architecture through to post-silicon validation.
• Experience in Tcl, Python, or Perl for developing automation flows.

Responsibilities

• Define and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, MBIST for huge memory instances, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG networks.
• Lead the complete DFT lifecycle from RTL planning to pattern handoff, own the schedule, resource allocation, and milestone tracking to ensure zero-defect delivery.
• Deploy next-generation DFT methodologies and automation flows to maximize test coverage, while minimizing test time, pattern count, and silicon area overhead.
• Collaborate with post silicon team, Physical Design and Power Architects.
• Support the post-silicon phase to achieve final Production Release Qualification (PRQ). Mentor senior technical staff, drive vendor EDA tool selection/qualification, and act as the primary technical liaison for DFT matters with stakeholders.

Skills

People management

Automation scripting

Leadership

Scripting (Tcl/Python/Perl)

Education

Bachelor's degree in Electrical/Computer Eng or equivalent

PhD in Electrical Engineering (preferred)

Tools

Siemens Tessent

Synopsys TestMAX/SMS

Cadence Modus

Job description

Share SoC DFT Technical Manager, Google Cloud

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical, Computer Engineering or equivalent practical experience.
• 10 years of experience in SoC DFT architecture and design.
• 10 years of experience in DFT protocols including Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).
• 10 years of experience with industry-standard EDA tools such as Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus.
• 4 years of people management experience developing employees and leading multiple SoC projects from RTL architecture through to post-silicon validation.
• Experience in Tcl, Python, or Perl for developing automation flows.

Preferred qualifications:

• PhD in Electrical Engineering with a focus on VLSI testing, fault tolerance, or reliability.
• Experience with advanced technology nodes (5nm/3nm), 2.5D/3D-IC packaging, or high-speed I/O (SerDes/DDR) testing methodologies.
• Experience managing global technical teams and driving vendor engagement.
• Ability to drive cross-functional timing closure, power analysis, and IR-drop mitigation for high-frequency designs.

About the job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Define and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, Memory BIST (MBIST) for huge memory instances, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks.
• Lead the complete DFT lifecycle from RTL planning to pattern handoff, own the schedule, resource allocation, and milestone tracking to ensure zero-defect delivery.
• Deploy next-generation DFT methodologies and automation flows to maximize test coverage, while minimizing test time, pattern count, and silicon area overhead.
• Collaborate with post silicon team, Physical Design and Power Architects.
• Support the post-silicon phase to achieve final Production Release Qualification (PRQ). Mentor senior technical staff, drive vendor EDA tool selection/qualification, and act as the primary technical liaison for DFT matters with stakeholders.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.