Senior DFT Design Engineer, Google Cloud

Google Inc.; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Google's AI/ML hardware team seeks a Senior DFT Design Engineer to shape DFT for TPU architectures powering large-scale AI workloads. You will design and validate DFT implementations across the verification flow, from circuit concepts to high-volume manufacturing, impacting Google’s data centers and users worldwide.

You will drive DFT architecture, test sequences, and production diagnostics, collaborating with cross-functional teams to ensure robust silicon solutions for AI accelerators.

Qualifications

• Bachelor's in Electrical Engineering or equivalent practical experience.
• 8+ years in implementation and validation of DFT technologies.
• Experience across DFT design, verification, specification, and architecture.

Responsibilities

• Develop DFT strategy and architecture for high-speed designs.
• Drive die-level DFT validation and fix TDRC violations.
• Insert DFT logic, boundary scan, TAP, and related IP blocks.
• Document DFT architecture and test sequences for production.
• Provide production and debug patterns to silicon teams.

Skills

DFT design

Verification

Mentoring

Problem solving

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree or PhD in EE/CE/CS (preferred)

Tools

DFT tools

ASIC DFT synthesis

Job description

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

• Bachelor's degree in Electrical Engineering, or a related field, or equivalent practical experience.
• 8 years of experience in the implementation and validation of DFT technologies.
• Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
• Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field.
• Experience in fault modeling.
• Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and DFT for multi die SoCs).
• Experience in SoC cycles, silicon bringup, and silicon debug activities.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Senior DFT Design Engineer, you will define, design, analyze the DFT implementation and flow, that supports the systems that are the heart of the world's largest and most powerful computing infrastructure. The team develops from the lowest levels of circuit design to large system design and sees those systems all the way through to high volume manufacturing. You will shape the machinery that goes into our data centers affecting millions of Google users.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for high speed iOS, Analog DFT).
• Develop and drive die level DFT validation strategy and complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
• Insert DFT logic, boundary scan, scan chains, DFT compression, logic BIST, TAP controller, clock control block, and other DFT IP blocks.
• Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
• Generate and deliver the production and debug patterns to Post Silicon Engineering team and run diagnosis for post silicon supports.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.