Silicon Design for Test Engineer

Google India Pvt Ltd; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Google India Pvt Ltd in Bengaluru is seeking a mid-level IC/DFT engineer to contribute to custom silicon solutions powering Google’s AI hardware platforms. You will work on DFT architectures, RTL testability, and SoC integration flows to ensure robust manufacturing and performance.

You will collaborate with cross-functional teams across design, verification, and DFT, participating in boot-up sequences, scan, BIST, and memory mbist activities, while driving quality and efficiency in the test flow.

Qualifications

• Bachelor's degree in Electrical Engineering or related field, or equivalent practical experience.
• 2 years of experience with analog or mixed-signal IC design.
• Experience with SoC design/integration flow and design automation.
• Experience with DFT technologies such as Scan, ATPG and MBIST.
• Experience with ASIC DFT synthesis, STA, simulation and verification flow.

Responsibilities

• Document DFT architecture and test sequences for boot-up.
• Participate in DFT logic insertion like scan and BIST at RTL and netlist levels.
• Perform DFT checks for scan coverage and memory Built-In Self Test (BIST).
• Plan SoC/IP/Subsystems DFT and support timing closure with PD/STA.

Skills

Analog/mixed-signal IC design

SoC design/integration flow

Design automation

DFT: Scan/ATPG/MBIST

ASIC DFT synthesis/STA/verification

Education

Bachelor's degree in Electrical Engineering or related field

Master's or PhD in EE/CE/CS or related field

Job description

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 2 years of experience with analog or mixed-signal Integrated Circuit (IC) design.
• Experience with system-on-chip design/integration flow, and design automation.
• Experience with Design for Test (DFT) technologies such as Scan, Algorithmic Test Pattern Generation (ATPG) and Memory Built in Self Test (MBIST).
• Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, STA, simulation, and verification flow.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
• Experience working with Automatic Test Equipment (ATE) engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
• Experience in System on a Chip (SoC) cycles, including silicon bring-up and silicon debug activities.
• Experience in fault modeling.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

Responsibilities

Document Design for Testability (DFT) architecture and test sequences, including boot-up sequence associated with test pins. Participate in DFT logic insertion like scan and BIST at Register-Transfer Level (RTL) and netlist level. Perform DFT checks for scan coverage and memory Built-In Self Test (BIST). Plan SoC/IP/Subsystems (SS) DFT and collaborate with cross-functional teams, DFT constraints development for timing closure and Physical Design (PD)/Static Timing Analysis (STA) support. Perform quality check flows like Lint, Clock Domain Crossing (CDC) of the DFT RTL in DFT modes. Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams.

Experience Level Mid Level