SoC DFT Technical Manager, Google Cloud

AI Chopping Block, Inc.; India; On-site; INR 600,000 - 900,000; Full time

Job summary

Google seeks an experienced DFT Architect to shape the future of AI/ML hardware acceleration, focusing on TPU design verification and integration within AI/ML systems. You will lead DFT development across multi-core SoCs, drive test methodologies, and collaborate with post-silicon teams to ensure robust production readiness.

You will mentor staff, manage global vendor engagements, and contribute to high-frequency design verification using Tcl, Python, or Perl automation.

Qualifications

• Bachelor's degree in Electrical, Computer Engineering or equivalent practical experience.
• 10 years of experience in SoC DFT architecture and design.
• 10 years of experience in DFT protocols including Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).
• 10 years of experience with industry-standard EDA tools such as Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus.
• 4 years of people management experience developing employees and leading multiple SoC projects from RTL architecture through to post-silicon validation.
• Experience in Tcl, Python, or Perl for developing automation flows.
• PhD in Electrical Engineering with a focus on VLSI testing (preferred).
• Experience with 5nm/3nm nodes, 2.5D/3D-IC packaging, or high-speed I/O testing (preferred).
• Experience managing global technical teams and driving vendor engagement (preferred).
• Ability to drive cross-functional timing closure, power analysis, and IR-drop mitigation.

Responsibilities

• Define and document the comprehensive DFT architecture for multi-core SoCs, including scan compression and MBIST.
• Lead the complete DFT lifecycle from RTL planning to pattern handoff, scheduling and milestones.
• Deploy next-generation DFT methodologies to maximize test coverage with minimized test time and area.
• Collaborate with post-silicon, PD and Power architecture teams.
• Mentor senior staff, drive vendor EDA tool selection and serve as DFT liaison.

Skills

DFT architecture

RTL design

DFT verification

Scripting (Tcl/Python/Perl)

Leadership

Education

Bachelor's degree in Electrical or Computer Engineering

PhD in Electrical Engineering

Tools

Siemens Tessent

Synopsys TestMAX/SMS

Cadence Modus

Job description

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

• Define and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, Memory BIST (MBIST) for huge memory instances, Functional BISTs, Analog components, Logic BIST, high-speed I/O loopback, and JTAG/IEEE 1149.1/1500/1687/1838 networks.
• Lead the complete DFT lifecycle from RTL planning to pattern handoff, own the schedule, resource allocation, and milestone tracking to ensure zero-defect delivery.
• Deploy next-generation DFT methodologies and automation flows to maximize test coverage, while minimizing test time, pattern count, and silicon area overhead.
• Collaborate with post silicon team, Physical Design and Power Architects.
• Support the post-silicon phase to achieve final Production Release Qualification (PRQ). Mentor senior technical staff, drive vendor EDA tool selection/qualification, and act as the primary technical liaison for DFT matters with stakeholders.

Minimum qualifications:

• Bachelor's degree in Electrical, Computer Engineering or equivalent practical experience.
• 10 years of experience in SoC DFT architecture and design.
• 10 years of experience in DFT protocols including Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1), and iJTAG (IEEE 1687).
• 10 years of experience with industry-standard EDA tools such as Siemens Tessent, Synopsys TestMAX/SMS, or Cadence Modus.
• 4 years of people management experience developing employees and leading multiple SoC projects from RTL architecture through to post-silicon validation.
• Experience in Tcl, Python, or Perl for developing automation flows.

Preferred qualifications:

• PhD in Electrical Engineering with a focus on VLSI testing, fault tolerance, or reliability.
• Experience with advanced technology nodes (5nm/3nm), 2.5D/3D-IC packaging, or high-speed I/O (SerDes/DDR) testing methodologies.
• Experience managing global technical teams and driving vendor engagement.
• Ability to drive cross-functional timing closure, power analysis, and IR-drop mitigation for high-frequency designs.