Physical Design and Implementation Engineer, Silicon Engineering

Google Inc.; Bengaluru; On-site; INR 4,000,000 - 6,400,000; Full time

Job summary

Google is seeking a Physical Design and Implementation Engineer in Silicon Engineering to own block or subsystem implementation of complex logic with emphasis on Power, Performance and Area (PPA). You will collaborate with RTL, DFT and IP teams to improve PPA and deploy AI-driven workflows to boost productivity and time to market.

The Platforms and Devices team at Google spans computing software platforms and first-party devices, delivering high-performance hardware experiences for users

Qualifications

• Bachelor's degree required in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 4 years of experience in physical design with two or more chip tape outs.
• Master's or PhD preferred with emphasis on computer architecture.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for GPU for the Tensor SOC.
• Manage block and full-chip level physical implementation and QoR (power, timing, area).
• Signoff convergence including STA, PDV, IR and EM.
• Optimize power, performance and area to achieve performance and cost.

Skills

Power optimization

Performance optimization

Area optimization

AI workflows in physical design

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Job description

Physical Design and Implementation Engineer, Silicon Engineering

Share Physical Design and Implementation Engineer, Silicon Engineering

X In most instances, this position requires in-person interviews as part of the hiring process.

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 4 years of experience in physical design with two or more chip tape outs.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience in power, performance and area optimization.
• Experience in high performance designs (CPUs, GPUs, DSPs or other compute etc.).
  

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Physical Design Engineer in the GPU Implementation team, you will own block or subsystem implementation of complex logic blocks with special focus on optimizing Power, Performance and Area (PPA). You will be working closely with the RTL, DFT and Foundation IP teams to improve PPA, deploy AI workflows to improve productivity, time to market and PPA.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for Graphics Processing Unit (GPU) for the Tensor SOC.

Manage block and full-chip level physical implementation and Quality of Results (QoR) (power, timing, area).

• Signoff convergence inclusing Static Timing Analysis (STA), Physical Design Verification (PDV), IR and EM (Electo-Migration).
• Optimize power, performance and area to achieve performance and cost.
• Reduce time to market and improve PPA through deployment of Artifical Intelligence (AI) physical design tools and workflows.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.