SoC Design Verification Engineer

Weekday AI (YC W21); Bengaluru; On-site; INR 1,600,000 - 6,800,000; Full time

Job summary

Weekday AI (YC W21) in Bengaluru is seeking a seasoned PCIe Gen5 verification engineer to verify high‑speed interfaces across IP, subsystem, SoC, and full‑chip levels. You will develop verification plans, build UVM environments, and drive sign‑off with strong debugging and coverage skills.

The role requires 4+ years in semiconductor design verification, hands‑on PCIe Gen5 experience, and deep knowledge of LTSSM, TLP, DLLP, and error handling.

Qualifications

• 4+ years of experience in semiconductor design verification.
• Mandatory: Strong hands-on PCIe Gen5 protocol verification.
• Proficiency in SystemVerilog and UVM.
• Experience in SoC/full-chip pre-silicon verification.

Responsibilities

• Develop detailed verification plans and test scenarios for PCIe Gen5 functionality.
• Build, enhance, and maintain SystemVerilog/UVM-based verification environments.
• Verify PCIe functionality across IP, subsystem, SoC, and full-chip levels.
• Develop and use Assertions and coverage models; drive regression and sign-off.

Skills

PCIe Gen5 verification

SystemVerilog

UVM

Debugging

Verification environments

Tools

SystemVerilog

UVM

Job description

Job Description:

This role is for one of the Weekdays clients

Salary range: Rs 1600000 - Rs 6800000 (ie INR 16-68 LPA)

Experience: 4+ yrs

Location: Bengaluru

Job Type: Full-time

We are looking for a skilledSoC Design Verification Engineerwith strong hands-on expertise inPCIe Gen5 protocol verificationto contribute to pre-silicon verification of complex semiconductor designs.

The role involves verifying PCIe functionality acrossIP, subsystem, SoC, and full-chip levelsusing SystemVerilog and UVM. The ideal candidate will have strong protocol knowledge, excellent debugging capabilities, and experience driving verification coverage and sign-off for complex SoC designs.

Key Responsibilities

• Develop detailedverification plans, test scenarios, and test strategiesfor PCIe Gen5 functionality.
• Build, enhance, and maintainSystemVerilog/UVM-based verification environments.
• Verify PCIe protocol functionality across IP, subsystem, SoC, and full-chip levels.
• Validate key PCIe features includingLTSSM, link training, TLP, DLLP, enumeration, configuration, and error handling.
• Perform functional, protocol compliance, and integration-level verification.
• DevelopSystemVerilog Assertions (SVA)and functional coverage models.
• Execute simulation regressions and analyze failures to drive coverage closure.
• Debug complexPCIe protocol, RTL, and integration issuesacross multiple design levels.
• Collaborate closely with RTL designers, architects, firmware engineers, and other verification teams.
• Identify verification gaps and contribute to improving test environments, methodologies, and automation.
• Track coverage, defects, and verification progress throughout the project lifecycle.
• SupportSoC/full-chip verification sign-offand ensure verification objectives are achieved before tape-out.

What Makes You a Great Fit

• 4+ years of experiencein semiconductor design verification or a related field.
• Mandatory: Strong hands-on experience in PCIe Gen5 protocol verification.
• Strong proficiency inSystemVerilog and UVM.
• Proven experience inSoC/full-chip pre-silicon verification.
• Strong understanding of PCIe architecture and protocol concepts, includingLTSSM, TLP, DLLP, link training, enumeration, configuration, and error handling.
• Strong hands-on experience withprotocol-level debuggingand RTL issue analysis.
• Experience developing verification plans, test scenarios, assertions, functional coverage, and regression environments.
• Demonstrated ability to drivecoverage closure and verification sign-off.
• Strong analytical and problem-solving skills with excellent attention to detail.
• Ability to collaborate effectively withRTL, architecture, firmware, and cross-functional verification teams.
• Experience working on complex SoC or high-speed interface verification projects is highly desirable.

Requirements: