Senior Design Verification Engineer

Silicon Patterns; Bengaluru; On-site; INR 1,500,000 - 2,100,000; Full time

Job summary

Silicon Patterns in Bengaluru, India is seeking a seasoned Design Verification Engineer with 5-12 years of experience to verify PCIe Controller IP and PHY designs for data center and AI/ML SoCs.

You will develop SystemVerilog/UVM based verification environments from scratch, run regressions, and collaborate with Design, Architecture, and Firmware teams on PCIe features such as TL, DLL, PL, L0/L1, ATS, DOE, AER, and test plans.

Qualifications

• 5-12 years of experience in design verification
• Strong expertise in PCIe Gen5/Gen6 verification
• Proficiency in SystemVerilog/UVM and TB development

Responsibilities

• Own verification of PCIe Gen5/Gen6 Controller IP (Root Complex / End Point)
• Develop SystemVerilog / UVM based verification environment from scratch and maintain TB
• Run regressions, debug failures, and drive coverage to closure
• Collaborate with Design, Architecture, and Firmware teams
• Experience with PIPE Interface verification (PIFP) and protocol analyzers is a plus

Skills

PCIe Gen5/Gen6

SystemVerilog/UVM

Verification environment

Test planning

Tools

LeCroy

Keysight

Protocol Analyzers

PIPE Interface (PIFP)

Job description

Experience: 5-12 Years

Employment Type:

Full-timeAbout The Role: We are looking for a highly skilled Design Verification Engineer with strong expertise in PCIe Protocol (Gen5 / Gen6) to join our high-speed interface IP / SoC verification team.

You will be responsible for verifying cutting-edge PCIe controller and PHY designs for next-gen data center and AI/ML SoCs.

Key Responsibilities:

Own verification of PCIe Gen5/Gen6 Controller IP (Root Complex / End Point / Dual Mode).

Develop SystemVerilog / UVM based verification environment from scratch and maintain existing TB.

Understand PCIe architecture and verify features like:Transaction Layer, Data Link Layer, Physical LayerFLIT Mode (Gen6), PAM4 Signaling, FEC, L0p, L1 PM SubstatesFlow Control, VC, QoS, Ordering, Completion HandlingLTSSM, Link Training, Equalization, Lane MarginingPower Management, SR-IOV, ATS, PASID, DOE, IDE (Security)PCIe Error Injection and Error Handling (AER, ECRC, Poisoned TLPs)Develop test-plans, coverage-plans, assertions (SVA) and functional coverage for Gen5/Gen6 features.Run regressions, debug failures with designers and drive to closure - 100% code & functional coverage.Work closely with Design, Architecture, and Firmware teams.Expertise in PIPE Interface verification (PIFP, 64b/128b/256b).Experience with Protocol Analyzers, LeCroy / Keysight Exercisers is a plus.