Principal RTL Design Engineer

STMicroelectronics; Greater Noida; On-site; INR 1,500,000 - 2,000,000; Full time

Job summary

STMicroelectronics seeks a skilled Design Engineer to lead the design and delivery of Core Subsystem for SoC generations. Candidates should have over 15 years of RTL design experience and expertise in SOC architecture.

Your responsibilities will include collaborating with systems architects, managing RTL delivery, and supporting silicon bring-up. Strong proficiency in ARM-based architecture and scripting in Python is essential.

This position encourages diverse candidates to apply.

Qualifications

• 15+ years of RTL design experience required.
• Hands-on experience in RTL coding, debugging, and verification.
• Strong experience in ARM-based SOC architecture and ASIC design flow.

Responsibilities

• Collaborate with systems architects to define SOC specifications.
• Lead end-to-end IP / Sub-system RTL delivery.
• Design and integrate standard interface protocols.

Skills

RTL design experience

ARM-based SOC architecture

Scripting in Python

Communication skills

Leadership skills

Education

Bachelor's or Master’s degree in Electronics/Electrical Engineering

Tools

EDA tools for synthesis

Job description

As part of the Platform Design team, the Design Engineer will lead and contribute to the design and delivery of Core Subsystem across multiple SoC generations.

Responsibilities

• Collaborate with systems architects and microarchitects to define high‑level, implementable SOC specifications.
• Own end‑to‑end IP / Sub‑system RTL delivery while analysing and optimising design for power, performance and area (PPA) targets.
• Work on IPs including ARM Cores, interconnect fabrics and memory controller IPs.
• Lead RTL design and integration of subsystems supporting complex architectures with multi‑core, multi‑reset domains.
• Demonstrate strong proficiency with frontend flows, including Lint, CDC, synthesis, DFT and static timing analysis (STA).
• Drive the development of robust safety, security and debug architectures for advanced SOCs with multiple interconnects.
• Design and integrate standard interface protocols such as AHB/AXI and memory interfaces such as RAM and Flash.
• Engage cross‑functionally with DFT, physical design, verification, emulation and validation teams to ensure first‑time‑right silicon and on‑time project delivery.
• Support silicon bring‑up, debug and post‑silicon performance analysis through detailed simulation and system‑level integration.
• Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift‑left the design cycle.
• Utilise scripting to manage design flows and automate repetitive tasks for improved efficiency.
• Mentor junior engineers and provide technical leadership and guidance across multiple design projects.
• Contribute to the innovation quotient of the team via patents and industry‑standard publications.

Qualifications

• Bachelor's or Master’s degree (or equivalent experience) in Electronics/Electrical Engineering with 15+ years of RTL design experience.
• Hands‑on experience in RTL coding, debugging, verification, synthesis and timing closure.
• Strong experience in ARM‑based SOC architecture and ASIC design flow.
• AMBA protocols (AXI, AHB, APB), clock/reset domains and memory subsystems.
• Experience with EDA tools for synthesis, Lint, CDC, RDC and timing analysis.
• Familiarity with formal verification techniques, static/dynamic power checks.
• Proficiency in scripting and automation using Python.
• Excellent leadership and communication skills.
• Experience working with global cross‑functional teams.
• Working knowledge of safety‑critical design flows in automotive systems; knowledge of ISO26262 is a plus.

ST is an equal‑opportunity employer and encourages diverse candidates to apply.