SOC Digital Design Architect

Mulya Technologies; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Mulya Technologies in Bengaluru seeks a senior SoC Architect to drive microarchitecture definition, MRD alignment, and top-level block diagrams for complex SoCs. You will shape fabrics, bridges, fuse/boot/security, and IP interfaces, coordinating with FPGA flows and SoC leads.

The role demands deep RTL experience, UPF, timing constraints, and end-to-end design reviews. You will write MAS/PRD documents, sign off reviews, and mentor the team on DV/DFT/PD plans to ensure production-ready silicon.

Qualifications

• 15+ years of relevant experience in SoC microarchitecture.
• Proven track record of micro-architecting and delivering complex SoCs to production.
• Expertise in RTL design, UPF, synthesis, verification, DFT and PD implementations.
• Ability to review and sign off design implementations.
• Hands-on with version control systems.

Responsibilities

• Responsibility for Micro architecture , Spec / MRD understanding
• Top level Architecture and Block Diagram
• SoC Fabrics, Protocol Bridges
• Fuse, Boot, Security
• IP planning and interfaces
• Pinout, ball mapping
• Systems and Test planning
• Design feasibility and PPA analysis
• Develop details for micro architecture for the target SoC to meet chip specifications.
• Write MAS / PRD document, drive alignment for IPs with reviews to signoff.
• Develop and work with the team to deliver RTL, UPF, timing constraints.
• Work with SoC lead to integrate the design and setup the FPGA flows
• Review DV, DFT and PD implementation plans for sign-off.

Skills

Verilog

VHDL

High Speed SerDes

Bus protocols

Clock management

Power management

Microarchitecture

RTL design

UPF

DFT/PD

Version control

Education

CS/EE/EC Engineering degree or postgraduate

Tools

Git

Job description

• Responsibility for Micro architecture , Spec / MRD understanding
• Top level Architecture and Block Diagram
• SoC Fabrics, Protocol Bridges
• Fuse, Boot, Security
• IP planning and interfaces
• Pinout, ball mapping
• Systems and Test planning
• Design feasibility and PPA analysis
• Develop details for micro architecture for the target SoC to meet chip specifications.
• Write MAS / PRD document, drive alignment for IPs with reviews to signoff.
• Develop and work with the team to deliver RTL, UPF, timing constraints.
• Work with SoC lead to integrate the design and setup the FPGA flows
• Review DV, DFT and PD implementation plans for sign-off.

Skills:

• Verilog, VHDL, High Speed SerDes protocols understanding, Bus protocols, Clock & power management etc.
• Proven track record of having Micro architected, Designed a complex SoC to production
• RTL design process: Specifying microarchitecture, developing RTL, linting, UPF coding, delivering synthesizable RTL, guiding Verification, DFT and PD implementations of the design.
• Awareness in comprehensive validation techniques of the specific design domain.
• Ability to review and signoff implementation of the design.
• Hands-on experience working with version control systems.
• Work with the FW development team for the design – as required.
• Scripting experience for efficiency and quality.

Education & Experience:

• CS/ EE/ EC Engineering Graduate or postgraduate with 15+ years of relevant experience.