SoC Design Director

Mulya Technologies; Bengaluru; On-site; INR 5,500,000 - 9,500,000; Full time

Job summary

Mulya Technologies in Bengaluru seeks a Digital Design professional with deep expertise in high-performance controller and bridge design, RTL implementation, and IP integration. You will own block-level and full-chip designs from architecture to GDS, ensuring timing closure and driving pre- and post-silicon verification.

The ideal candidate has 15+ years of digital design experience, with strong RTL, synthesis, and verification skills, plus hands-on PCIe/IP experience and scripting capabilities.

Qualifications

• Bachelor’s degree in Electronics/Electrical engineering.
• 15+ years of digital design experience, with processor and full-chip focus.
• Expertise in RTL development, synthesis, and timing closure.
• Experience with front-end design and design verification.

Responsibilities

• Design and implement high-performance digital solutions including RTL development and synthesis.
• Collaborate on IP integration for processor IPs and peripherals.
• Own block-level and full-chip designs from architecture to GDS, with timing closure.
• Utilize Synopsys/Cadence tools and drive pre- and post-silicon debug.

Skills

RTL development

Synthesis

UVM verification

SystemVerilog

Processor IP integration

Timing closure

Python/Perl scripting

ASIC/SoC design

PCIe/IP blocks

Education

Bachelor’s in Electronics/Electrical Engineering

Master’s degree (preferred)

Tools

Synopsys

Cadence

UVM

Job description

Top30 Semiconductor Organization in the world

Role Overvie w

We are seeking a Digital Design professional with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Key Responsibili ties

• Design and implement high-performance digital solutions, including RTL development and synthesis.Collaborate with cross-functional teams on IP integration for processor IPs and peripherals
• Deep knowledge of processor boot process and peripheral implementation with boot firmware inmind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤16nm.Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug.Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verificationflows
• Basic Qualifications / Experience Level
• Bachelor’s in Electronics/Electrical engineering (Master's prefe
• rred).Minimum 15+ years of digital design experience, with focus on processor, peripherals and full chip implementation.Proven expertise in RTL development, synthesis, and timing closure.Experience with front-end design, gate-level simulations, and design verification.Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused atttude.

Required Expertise

Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced

nodes (Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O

cycles .Hands-on experience with processor IP (

ARM/ARC)

Experience of working on PCIe is a must

.Hands-on pre-silicon and post-silicon implementing peripherals for I2C/

SPI/UART

Hands-on experience with complex DMA engines and FW interaction

.Strong proficiency in System Verilog/Verilog and scripting (Pytho

n/Perl)

.Experience with block-level and full-chip design at advanced nodes (≤ 16nm)

.Silicon bring-up and post-silicon debug experience

.Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification

.Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude.

Preferred Experience

• Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation

is a plus

.Knowledge of system-level design with ARM/ARC/RISC-V processorssub systems

Experience of working on PCIe/UAL isa big plus

.Understanding of PAD design, DFT, and floor planning

.Experience in synthesis, and timing closure is a big plus

.Experience with NIC, switch, or storage product development

.Familiarity with working in design and verification workflows in a CI/CD environment.

Skils