PCIe IP Verification Engineer

NVIDIA Gruppe; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

NVIDIA Gruppe is seeking a Senior Verification Engineer in Bengaluru, India to verify cutting-edge PCI Express controllers for GPUs and SOCs. You will be responsible for ASIC design verification, using methodologies like UVM while collaborating with multidisciplinary teams.

The ideal candidate has a B.Tech./M.Tech, 2+ years of relevant experience, and proficiency with Verilog/SystemVerilog. Join a dynamic company impacting various tech domains including AI and self-driving cars.

Qualifications

• 2+ years of relevant experience in ASIC verification.
• Expertise in comprehensive verification of IP or interconnect protocols.
• Experience in coverage-driven verification methodology.

Responsibilities

• Verify ASIC design, architecture, and micro-architecture of PCIE controllers.
• Develop test plans and verify design correctness.
• Collaborate with architects, designers, and verification teams.

Skills

Verification at Unit/Sub-system/SOC level

Verilog

SystemVerilog

PCIE protocol knowledge

Scripting skills (e.g., Perl, Python)

Education

B.Tech./M.Tech or equivalent

Tools

UVM/VMM

Job description

NVIDIA is seeking an elite Senior Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

What you’ll be doing:

• Be responsible for verification of the ASIC design, architecture, golden models and micro-architecture of PCIE controllers at IP/sub-system levels using state-of-the-art verification methodologies such as UVM.
• Build reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
• Expected to understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design.
• You will be collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.

What we need to see:

• B.Tech./ M.Tech or equivalent experience
• 2+ years of relevant experience
• Experience in verification at Unit/Sub-system/SOC level and expertise in Verilog and SystemVerilog
• Expertise in comprehensive verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA)
• Experience in developing and working in functional coverage based constrained random verification environments
• Background in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug

Ways to stand out from the crowd:

• Excellent knowledge of PCIE protocol - Gen3 and above
• Good understanding of the system level architecture of PCIE/CXL-based designs
• Perl, Python or similar scripting and SW programming language experience
• Good debugging and analytical skills
• Good interpersonal skills & dream to work as a great teammate

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.