Senior Staff Engineer - Power Integrity

MediaTek Research Lab Inc.; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

MediaTek Research Lab Inc. is seeking a Senior Staff Engineer to lead PI/IR drop analysis for subsystems and full SoCs. You will drive EM and IR analysis across power modes, troubleshoot issues, and propose fixes in collaboration with PD, timing and packaging teams.

You will also automate reporting, set up the PI environment, and mentor a small team of engineers to improve throughput and quality on 16nm and below nodes.

Qualifications

• 12+ years of EM and IR analysis with PD and timing exposure.
• Hands-on with RedHawk-SC or Voltus, preferably both.
• Leading block- or chip-level IR/EM analysis.
• Automation skills in TCL/Perl/awk/Python/Unix shell.
• Debugging inputs like design data, library info, package, and RDL routing.
• Experience to lead a team of 3–4 and mentor juniors.
• Worked on 16nm or smaller nodes, with low-power designs.
• Exposure to PD and timing tools: Innovus, Tempus, ICCompiler2, PrimeTime.

Responsibilities

• Lead Signoff level IR drop and EM analysis for subsystems and SoC.
• Run EM and static/dynamic IR analysis across modes and power scenarios; identify root causes.
• Provide fixes and ECOs; communicate feedback to Power, package, PD teams.
• Automate reporting, debugging, and fixing suggestions.
• Set up and maintain the PI analysis environment.
• Mentor junior team members to improve productivity and output quality.

Skills

EM analysis

IR analysis

Power integrity

Automation (TCL/Perl/Python/Unix)

Leadership

Team mentoring

Low power design (multi-voltage)

Physical design exposure

Node 16nm and below

Tools

RedHawk-SC

Voltus

Innovus

Tempus

ICCompiler2

PrimeTime

Job description

Senior Staff Engineer - Power Integrity / IR drop analysis

Roles & Responsibilities

• The PI Signoff / IR Drop Analysis Lead is responsible for Signoff level IR drop, Power/Signal EM analysis of a Subsystem and Full SoC
• He is responsible for running EM and Static/Dynamic IR analysis for various modes/power scenarios, root cause failures, provide fixing solutions
• Responsible for EM and IR drop analysis (vector and vectorless) for both block and full chip designs for various power modes and scenarios.
• Provide feedback / improvement / fixing suggestions to various stake holders like owners for Power, package, pattern, physical design, timing, etc
• Analyze weakness area(s) in the design and provide fixing solutions.
• Automation for reporting, debug, fixing suggestions/ECOs.
• Setting up and Maintaining the environment for the overall PI analysis
• Provide training to junior folks in the team to enhance their productivity and to extract quality work.

Main Requirements and Qualifications

• The candidate must have:
• 12+ years of experience in EM and IR analysis with exposure to Physical Design and timing analysis
• Hands-on experience on RedHawk-SC or Voltus, preferably both
• Hands-on experience on Low power, multi voltage, power off (MTCMOS), and mixed signal designs
• Experience in leading block level or chip level IR/EM analysis
• Ability to debug and resolve issues with inputs like – design data, library info, package, bump locations/RDL routing
• Automation skills in TCL/Perl/awk/Python/Unix shell
• Team player who is able to autonomously plan and perform tasks
• Experience to Lead a team of 3-4 folks, by prioritizing and assigning tasks, guide and mentor juniors on the job
• Worked on technologies 16nm and below, preferably on N7 and lower nodes
• Exposure on designing power mesh especially on low power, power shut off designs
• Some exposure to Physical Design and timing analysis tools like (Innovus, Tempus, ICCompiler2, PrimeTime)