MTS HIG-HBM-LAYOUT

Micron Technology; Hyderabad; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

Micron Technology is seeking a senior Semiconductor Design Engineer MTS to lead end-to-end analog/mixed-signal layout for HBM products. You will own full-chip technical decisions, drive scheduling and cross-functional collaboration to meet performance, power and area targets.

Responsibilities include mentoring the layout team, conducting reviews, adopting AI/automation where possible, and ensuring on-time delivery across multiple programs while maintaining quality and documentation standards.

Qualifications

• 18+ years of analog/custom layout experience in advanced CMOS.
• 4+ years leading teams and projects; tape-out experience.
• Multi-project leadership across time zones and teams.
• Cadence VLE/VXL and Calibre DRC/LVS proficiency.
• Strong layout, floorplanning and manual routing skills.
• Excellent verbal and written communication.

Responsibilities

• Lead end-to-end layout execution for HBM products.
• Own full-chip technical decisions covering analog, digital, memory and PPA.
• Mentor layout team, conduct design reviews and enable capability development.
• Ensure timely delivery with high quality and proper documentation.

Skills

Layout design

Team leadership

Project management

Communication

Education

BE/MTech in Electronics/VLSI

Tools

Cadence VLE/VXL

Calibre DRC/LVS

Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Role and Responsibilities

• Lead end-to-end layout execution of analog, mixed-signal, custom digital blocks and full-chip integration for HBM products.
• Own full-chip technical decisions covering analog, digital, memory, ESD, EM/IR and ensure optimal performance, power, and area (PPA).
• Technical Expertise: Hands-on experience in layout design of critical Memory /Analog and mixed-signal blocks such as: Array Layout, Decoder, Control logic , IOs , PLLs , ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers.
• Drive project planning and execution, including area/time estimation, scheduling, task delegation, and milestone tracking across multiple concurrent programs.
• Ensure timely delivery with quality, responsible for block-level and full-chip layouts meeting schedule commitments and quality expectations.
• Perform and oversee layout verification activities including LVS, DRC, Antenna checks, and ensure closure with proper documentation and audits.
• Lead and mentor the layout team, guiding junior engineers on sub-block execution, conducting design reviews, and enabling capability development.
• Drive innovation and productivity improvements, including adoption of AI/automation to reduce layout effort, improve turnaround time, and enhance quality.
• Collaborate with global cross-functional teams (Design, Verification, IP, Packaging) and ensure strong communication for project alignment and success.
• Support customer and product integration needs, including specification alignment, design clarifications, and successful implementation of Micron solutions.
• Contribute to organizational growth and leadership initiatives, including team building, hiring, performance management, and representing Micron in industry engagements.

Qualification/Requirements

• 18 + year experience in analog/custom layout in advanced CMOS process.
• Minimum 4+ years developing teams and project experience.
• Should have experience in leading multiple project and Tape-out.
• Expertise in Cadence VLE/VXL and Calibre DRC/LVS is a must.
• Must have strong skills in layout and floor planning skills and manual routing.
• Strong ability to build, and continuously develop a premier analog/mixed-signal layout team
• Experienced in running multiple Custom IC layout projects
• Excellent verbal and written communication skills required.
• Capable of working in a multi-functional, multi-site team environment in multiple time zones.

Education

• BE or MTech in Electronic/VLSI Engineering.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

Job Profile(s):

• Semiconductor Design Eng MTS

Relocation level: (TBD)

Before Getting Started

Please review Micron’s Internal Job Application Policy on your regional PeopleNow Career Opportunities page before searching and applying for jobs. Note in particular that:

• Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence.
• If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.