Principal Layout Designer

Micron Technology, Inc; Hyderabad; On-site; INR 1,500,000 - 3,000,000; Full time

Job summary

Micron Technology, Inc. is seeking a Principal Layout Designer with 10+ years of layout experience to advance critical Core and Periphery blocks for next‑gen memory products.

You will craft high‑quality layouts using Cadence VXL and collaborate across TD, Design and CAD teams to meet tight tape‑out schedules. You should have strong LVS/DRC debugging skills, deep understanding of core/pitch fundamentals, and the ability to mentor junior engineers while driving innovation across memory generations

Qualifications

• Ability to understand design constraints and implement high-quality layouts.
• Strong debug and problem-solving skills for LVS, DRC & Layout issues.
• Experience creating layout of Core/Pitch blocks (Array, Row/decoder & Column Decoder).
• Good understanding of Core/Pitch Layout fundamentals such as BL & WL pitch.

Responsibilities

• Deliver major level blocks including signal and floorplan to the Core/Pitch and Periphery area.
• Coordinate with TD, Design and CAD teams to apply multiple layout techniques for the design and verification of Array, Digital and Analog circuits.
• Execute secondary layout tasks such as ECO, LCO and DFM.
• Mentor junior team members and drive innovation into future memory generations.

Skills

Layout design understanding

Debug & problem-solving

Coordination with design & CAD teams

Mentoring juniors

Tools

Cadence VXL

Job description

Req. ID: JR112356 Principal Layout Designer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Principal Layout Designer (10+ years of experience in layout)

• You must have the ability to understand design constraints and implement high-quality layouts.
• You must be proficient using Cadence VXL on periphery blocks.
• You must have strong debug and problem-solving skills for LVS, DRC & Layout issues.
• You must have hands‑on experience in creating layout of critical Core/Pitch blocks such as Array, Row decoder & Column Decoder.
• You must have good understanding of Core/Pitch Layout fundamentals such as BL & WL pitch, and a feasibility acumen for developing WL & BL drivers & pre-drivers.
• You must have good experience of Chip Level Integration and Die Size calculations.
• You must have a good understanding of the Design rules and deliver with quality layout.
• You must deliver major level blocks, including signal and floorplan, to the Core/Pitch and Periphery area.
• You will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of Array, Digital and Analog circuits.
• You must execute secondary layout tasks such as ECO, LCO and DFM.
• You will be responsible for coordinating with TD, Design, CAD and layout teams to deliver on schedule with quality.
• You must demonstrate a strong ability to debug problems, find effective solutions, and negotiate with the engineering staff. You will be required to meet all engineering and process related criteria needed for an assigned NAND product.
• You will organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution.
• You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tape‑out processes and procedures.
• You should be able to mentor Junior team members.
• You must drive innovation into the future Memory generations within a dynamic work environment.
• Multiple Tape out support experience will be an added advantage.
• You must have a good understanding of automation and leveraging AI tool proficiency to enable your work.

Job Profile(s):

Semiconductor Design Engineer 5

Relocation level: (TBD)

Before Getting Started

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• If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.