Senior Design Verification Engineer

Weekday AI (YC W21); Hyderabad; On-site; INR 1,500,000 - 1,800,000; Full time

Job summary

Weekday AI invites a Senior Design Verification Engineer to drive CPU/SoC verification across architectures in a full-time role in India. The candidate should have 5+ years of ASIC/SoC verification experience and strong SystemVerilog/UVM skills.

Expect hands-on testbench development and collaboration with RTL teams for robust verification results. Location includes Bengaluru and Hyderabad, with on-site work and exposure to AXI/CHI protocols, emulation, and advanced verification methods.

Qualifications

• 5+ years total ASIC/SoC Design Verification experience.
• At least 2+ years dedicated CPU verification experience.
• Hands-on SystemVerilog and UVM expertise.
• CPU architecture knowledge including RISC-V/ARM/x86 cores.

Responsibilities

• Develop and execute CPU/SoC verification strategies and test plans.
• Build, enhance, and maintain UVM verification environments with SystemVerilog.
• Develop reusable verification components, sequences, scoreboards, monitors, and coverage models.
• Verify CPU functionality across architectures (RISC-V, ARM, x86, or custom cores).
• Create test scenarios for CPU pipelines, interrupts, memory ordering, and architecture behavior.
• Verify cache coherency and CPU/SoC subsystem interactions.
• Verify AMBA protocols (AXI, AHB, ACE, CHI) and high-speed interfaces.
• Run simulations with VCS/Xcelium/Questa; debug RTL/testbench issues and identify root causes.
• Develop functional/coverage models and track verification completeness.
• Mentor junior engineers and contribute to verification methodology.
• Assist with power-aware verification (UPF/CPF) when applicable.

Skills

SystemVerilog

UVM

CPU verification

ASIC/SoC verification

RISC-V

ARM

x86

AMBA protocols

VCS

Xcelium

Questa

Python

Debugging

Education

B.Tech/M.Tech in Electronics, VLSI, Computer Engineering

Tools

VCS

Xcelium

Questa

Palladium

Veloce

Zebu

Job description

Job Description:

This role is for one of the Weekdays clients

Salary range: Rs 1500000 - Rs 1800000 (ie INR 15-18 LPA)

Experience: 5+ yrs

Location: Bengaluru, Hyderabad, Telangana, India

Job Type: Full-time

We are looking for an experiencedSenior Design Verification Engineerto drive verification activities forCPU and SoC subsystemsusing industry-standard verification methodologies and tools. The role requires strong hands-on expertise inSystemVerilog, UVM, CPU verification, and ASIC/SoC design verification, with practical experience across modern processor architectures such asRISC-V, ARM, x86, or custom CPU cores.

The ideal candidate will have a strong understanding of CPU architecture, cache coherency, pipeline execution, AMBA protocols, and verification environments, with the ability to develop robust testbenches, debug complex failures, and contribute to verification strategy and execution.

KEY RESPONSIBILITIES

• Develop and execute comprehensiveCPU and SoC design verificationstrategies and test plans.


• Build, enhance, and maintainUVM-based verification environmentsusing SystemVerilog.


• Develop reusable verification components, sequences, scoreboards, monitors, checkers, and coverage models.


• Verify CPU functionality across architectures such asRISC-V, ARM, x86, or custom processor cores.


• Develop test scenarios covering CPU pipeline execution, interrupts, exceptions, memory ordering, and architectural behaviour.


• Verifycache coherencyand CPU/SoC subsystem interactions.


• Develop and execute verification forAMBA protocols, including AXI, AHB, ACE, and CHI.


• Run simulations using industry-standard EDA tools such asVCS, Xcelium, and Questa.


• Analyse simulation failures, debug complex functional issues, and identify root causes in RTL, testbench, or design behaviour.


• Develop functional and code coverage models and track verification completeness.


• Collaborate with RTL designers and architects to understand specifications and resolve design issues.


• Develop automation and productivity tools usingPython, Perl, and TCL.


• Write and execute low-level tests usingRISC-V or ARM Assembly and C/C++where required.


• Support regression infrastructure, test execution, failure triage, and verification reporting.


• Contribute to verification methodology improvements, reusable infrastructure, and automation initiatives.


• Support advanced verification activities involvingpower-aware verification using UPF/CPF, where applicable.


• Contribute to verification of high-speed interfaces such asPCIe, CXL, and DDR.


• Support emulation-based verification using platforms such asPalladium, Veloce, or Zebu, where required.


• Mentor junior verification engineers and contribute to technical reviews and knowledge sharing.

WHAT MAKES YOU A GREAT FIT

• 5+ years of total ASIC/SoC Design Verification experience, including at least2+ years of dedicated CPU verificationexperience.


• Strong hands-on expertise inSystemVerilog and UVM.


• Practical CPU verification experience withRISC-V, ARM, x86, or custom processor architectures.


• Strong understanding ofCPU architecture, pipeline execution, cache coherency, memory ordering, interrupts, and exceptions.


• Hands-on experience withAMBA protocols, particularly AXI, AHB, ACE, and/or CHI.


• Experience with EDA simulation tools such asSynopsys VCS, Cadence Xcelium, or Siemens Questa.


• Strong experience developing UVM testbenches, sequences, monitors, scoreboards, assertions, and coverage models.


• Working knowledge ofRISC-V/ARM Assembly, C/C++, Python, Perl, and TCL scripting.


• Understanding ofout-of-order executionand modern processor verification concepts.


• Strong debugging, analytical, and problem-solving skills.


• Ability to analyse complex simulation failures and drive issues through resolution.


• Strong communication and collaboration skills across Design, Architecture, Firmware, and Verification teams.


• Experience withUPF/CPF and power-aware verification is an advantage.


• Exposure toPCIe, CXL, DDR, or other high-speed interconnects is an advantage.


• Experience withPalladium, Veloce, Zebu, or other emulation platforms is an advantage.


• B.Tech/M.Tech inElectronics, VLSI, Computer Engineering, or a related discipline is preferred.

Requirements: