Lead-Design Verification / RTL Design / DFT

FyndBridge Consultants & Advisors; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

FyndBridge Consultants & Advisors in Bengaluru, India, is seeking senior design verification and RTL/DFT architects for a US-headquartered semiconductor startup. The role spans SoC design verification, RTL design, and DFT architecture, with ownership of verification sign-off and cross-functional collaboration with RTL, architecture, and physical design teams.

You will lead verification strategies, test plans, and reusable environments, working on SystemVerilog, UVM, ATPG/MBIST, and

Qualifications

• 15+ years of experience in design verification of complex digital systems, ASICs, and SoCs.
• Strong analytical, debugging, and problem-solving skills.
• Deep understanding of computer architecture, microarchitecture, SoC architecture, and digital design fundamentals.
• Hands-on expertise in SystemVerilog, UVM, C/C++, assertions, constrained-random verification, and coverage-driven verification methodologies.
• Familiarity with formal verification techniques and industry-standard formal verification tools.
• Experience verifying complex subsystems such as memory systems, interconnect fabrics, caches, DMA engines, processors, or AI accelerator architectures.
• Experience developing verification strategies, test plans, testbenches, and reusable verification environments.
• Ability to drive functional and code coverage closure, debug complex design issues, and ensure verification sign-off.
• Experience leading design verification teams and collaborating with RTL, architecture, and physical design teams is preferred.

Skills

SystemVerilog

UVM

C/C++

Assertions

Formal verification

SoC architecture

Microarchitecture

Debugging

Test plan development

Team leadership

Tools

EDA tools

Verification tools

Job description

Our client is a US-headquartered semiconductor start-up that designs and develops ultra-low-power silicon and software. The company is building its next-generation products from the ground up, offering engineers the opportunity to work on a new System-on-Chip (SoC) for Physical AI with genuine ownership of the design, rather than making incremental changes to existing products.

Engineers will work alongside a founding team with extensive Silicon Valley experience, backed by significant early-stage funding. The company's differentiated low-power technology presents an opportunity to develop innovative semiconductor solutions for next-generation AI applications.

As part of its expansion, the company plans to establish and scale its semiconductor engineering capabilities in India across SoC and microarchitecture, RTL design, design verification, physical design, custom circuit design, and semiconductor software.

Key Skills and Qualifications

• 15+ years of experience in design verification of complex digital systems, ASICs, and SoCs.
• Strong analytical, debugging, and problem-solving skills.
• Deep understanding of computer architecture, microarchitecture, SoC architecture, and digital design fundamentals.
• Hands-on expertise in SystemVerilog, UVM, C/C++, assertions, constrained-random verification, and coverage-driven verification methodologies.
• Familiarity with formal verification techniques and industry-standard formal verification tools.
• Experience verifying complex subsystems such as memory systems, interconnect fabrics, caches, DMA engines, processors, or AI accelerator architectures.
• Experience developing verification strategies, test plans, testbenches, and reusable verification environments.
• Ability to drive functional and code coverage closure, debug complex design issues, and ensure verification sign-off.
• Experience leading design verification teams and collaborating with RTL, architecture, and physical design teams is preferred.

Key Skills and Qualifications

• 15+ years of experience in RTL design for complex digital systems, ASICs, and SoCs.
• Strong understanding of computer architecture, microarchitecture, SoC architecture, and digital design fundamentals.
• Hands-on expertise in Verilog/SystemVerilog and modern RTL design methodologies.
• Experience translating architectural specifications into synthesizable, high-quality RTL.
• Strong understanding of performance, power, and area (PPA) trade-offs and RTL optimization techniques.
• Experience designing complex subsystems involving processors, caches, memory systems, interconnects, DMA engines, or AI accelerators.
• Familiarity with synthesis, timing constraints, linting, clock-domain crossing (CDC), reset-domain crossing (RDC), and RTL quality checks.
• Understanding of low-power design methodologies and hardware/software co-design.
• Experience collaborating with architecture, verification, physical design, and DFT teams to achieve design closure.
• Proven ability to lead RTL design teams and drive complex SoC development from architecture through implementation.

Key Skills and Qualifications

• 15+ years of experience in DFT architecture, implementation, and sign-off for ASIC/SoC designs.
• Strong background in compute, AI, high-performance SoCs, networking, processors, GPUs, accelerators, or other complex digital silicon designs.
• Proven experience defining and leading DFT strategies for large-scale ASIC/SoC programs, from concept through silicon production.
• Deep expertise in scan design, scan compression, Automatic Test Pattern Generation (ATPG), Memory Built-In Self-Test (MBIST), Logic Built-In Self-Test (LBIST), JTAG, boundary scan, IJTAG, test access architecture, and fault simulation.
• Hands-on experience in ATPG pattern generation, test coverage closure, pattern validation, fault diagnosis, and silicon correlation.
• Experience leading DFT teams and managing cross-functional execution across multiple projects or design programs.
• Strong experience in post-silicon debug, yield improvement, failure diagnosis, production test support, and field failure analysis.
• Good understanding of DFT implications for RTL design, physical design, timing closure, low-power implementation, and sign-off.
• Experience with industry-standard EDA tools for scan insertion, compression, ATPG, MBIST/LBIST, verification, and diagnosis.
• Familiarity with advanced fault models and test methodologies, including stuck-at, transition-delay, path-delay, at-speed, and cell‑aware testing, as well as timing‑aware ATPG.