RTL Design Engineer

PQAngels Technologies Pvt. Ltd; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

PQAngels Technologies Pvt. Ltd in Bengaluru is seeking an experienced RTL Design Engineer to contribute to architecture, micro-architecture, and RTL implementation of high-performance IPs and SoC subsystems.

You will work with architects and verification engineers across GPU, ARM CPU/IP, Ethernet, and encryption/security streams to deliver silicon-ready designs. The role requires 5+ years of RTL design, deep knowledge of Verilog/SystemVerilog, AMBA protocols, and collaboration across

Qualifications

• Bachelor's or Master's in Electrical/Electronics or Computer Engineering.
• 5+ years of hands-on RTL design using Verilog/SystemVerilog.
• Strong understanding of timing, CDC, and low-power techniques.
• Experience with EDA tools for simulation, synthesis and lint/CDC analysis.
• Familiarity with AMBA protocols (AXI, AHB, APB) and NoC architectures.
• Excellent written and verbal communication skills.

Responsibilities

• Design, code, and optimize RTL for digital IPs and SoC subsystems.
• Translate micro-architecture specs into synthesizable RTL.
• Collaborate with verification teams to define test plans and debug RTL issues.
• Perform RTL-level simulation, lint checks, and CDC/RDC analysis.
• Support synthesis, timing closure, and physical design handoff with backend teams.
• Debug silicon bring-up issues and assist post-silicon validation.
• Participate in design and code reviews and document specs.

Skills

RTL design

Verilog/SystemVerilog

Digital design fundamentals

AMBA protocols

cross-functional collaboration

Education

Bachelor's/Master's degree in Electrical/Electronics or Computer Engineering

Tools

VCS

Design Compiler

Spyglass

Job description

PQAngels Technologies Pvt. Ltd | Full time

PQAngels Technologies is a specialized in building high-performance engineering teams for the Post Quantum era of innovation. The company connects cutting-edge technology organizations with highly skilled professionals in Semiconductors, Cloud Computing, and Data Storage ecosystems. PQAngels Technologies focuses on niche engineering roles, enabling clients to innovate faster while offering candidates access to advanced projects and career growth. Applicants can expect to work with leading global tech companies and be part of teams driving next-generation hardware and software solutions.

Job Description

About PQAngels Technologies

PQAngels Technologies is a semiconductor design and verification company specializing in high-performance IP and SoC development across GPU, ARM, Ethernet, and security/encryption domains. We partner with leading silicon companies to deliver robust, silicon-proven RTL and verification solutions.

About the Role

We are looking for an experienced RTL Design Engineer to join our design team and contribute to the architecture, micro-architecture, and RTL implementation of high-performance IPs and SoC subsystems. You will work closely with architects and verification engineers across GPU, ARM CPU/IP, Ethernet, and encryption/security work streams to deliver silicon-ready designs.

Key Responsibilities

• Design, code, and optimize RTL (Verilog/SystemVerilog) for digital IPs and SoC subsystems.
  
• Translate micro-architecture specifications into synthesizable, low-power, high-performance RTL.
  
• Collaborate with verification teams to define test plans, debug RTL issues, and close functional coverage.
  
• Perform RTL-level simulation, lint checks (e.g., Spyglass), and CDC/RDC analysis.
  
• Work on cache/coherency, NoC, and interconnect protocol implementation (AMBA, CHI, AXI, AHB, APB).
  
• Support synthesis, timing closure, and physical design handoff in collaboration with backend teams.
  
• Debug silicon bring-up issues and support post-silicon validation as needed.
  
• Participate in design and code reviews, ensuring adherence to coding guidelines and best practices.
  
• Document micro-architecture, design specifications, and verification collateral.
  

Requirements

Required Skills & Qualifications

• Bachelor's/Master's degree in Electrical/Electronics Engineering, Computer Engineering, or related field.
  
• 5+ years of hands-on experience in RTL design using Verilog/SystemVerilog.
  
• Strong understanding of digital design fundamentals — timing, clock domain crossing (CDC), low-power design techniques.
  
• Experience with industry-standard EDA tools for simulation, synthesis, and lint/CDC analysis (e.g., VCS, Design Compiler, Spyglass).
  
• Solid working knowledge of AMBA protocols (AXI, AHB, APB) and on-chip interconnect/NoC architectures.
  
• Familiarity with ARM CPU/IP subsystems, CHI coherency protocol, or Ethernet/SerDes controller design (domain-specific expertise a plus).
  
• Strong debugging skills and ability to work with cross-functional design, verification, and physical design teams.
  
• Excellent written and verbal communication skills.
  

Preferred Qualifications

• Experience in one or more of the following domains: GPU sub-system design, ARM CPU/IP integration, Ethernet controller/protocol design, or encryption/security IP (AES-XTS, MACsec).
  
• Exposure to low-power design methodologies (UPF/CPF).
  
• Prior experience taking designs from RTL through synthesis and timing closure.
  
• Experience with scripting languages (Python, Perl, TCL) for design automation.
  

What We Offer

• Opportunity to work on cutting-edge silicon IPs across GPU, ARM, Ethernet, and security domains.
  
• Collaborative, engineering-driven culture with direct exposure to end-to-end chip design flow.
  
• Competitive compensation aligned with experience and expertise.