Senior RTL Design Engineer

7Rays Semiconductors; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

7Rays Semiconductors is seeking a Lint/CDC Design Lead with 5+ years of VLSI experience. You will lead RTL implementation for high-speed IP blocks, optimize timing, and drive CDC/Lint closures while coordinating with cross-functional teams.

The role emphasizes innovative problem solving, thorough documentation, and proactive communication to deliver robust digital designs at advanced nodes.

Qualifications

• 5+ years of relevant experience in VLSI design.
• Strong RTL design skills for low-node technologies (3/4/7nm).
• Experience in micro-architecture and implementing complex IP blocks.
• Expertise in timing analysis and path optimization across ASIC flows.
• Experience with AXI4/5 and CHI interfaces.
• RTL implementation of PCIe/CXL, Ethernet, UCIe, UAL, and DDR/HBM/LPDDR.
• Closure of RTL blocks with CDC/RDC/Lint checks.
• A proactive team player who can drive closure with clear documentation.
• Ability to define innovative design solutions and lead discussions.

Skills

RTL design

Digital IP

Timing analysis

AXI4/5

CHI interfaces

PCIe/CXL

Ethernet

UCIe

UAL

DDR/HBM/LPDDR

CDC/RDC/Lint

ASIC design closure

Job description

At 7Rays Semiconductors (https://7rayssemi.com/), we provide end-to-end VLSI design solutions to help our clients achieve execution excellence. Our team of experts specializes in architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation using the latest technologies and methodologies

We work closely with our clients, building effective partnerships to deliver high-quality solutions tailored to their needs. With a proven track record of successful projects, we are committed to excellence and innovation in semiconductor design.

Job Title: Lint/CDC Design Lead

• Experience: 5+ years of relevant experience
• Strong in digital IP design using RTL for lower technology nodes [3/4/7nm].
• Experience in micro architect and implementation of complex IP blocks for high-speed designs.
• Optimization of digital logic by analysing timing reports at various stages of ASIC design cycles and defining solutions for path.
• Experience in developing modules for AXI4/5, CHI interfaces.
• Experience in RTL implementation of PCIe/CXL, Ethernet, UCIE , UAL, DDR/HBM/LPDDR and AXI bridging layer.
• Experience in the closure of RTL blocks with quality checks, CDC/RDC/Lint.
• Define and propose innovative solutions to the problem.
• Good team player, proactive in communications, lead proposed solutions to closure.
• Documentation on design approaches, discuss it within the team, come up with conclusive approaches and drive it.
• Co-work with other functional teams on project