Senior Lead RTL Design Engineer

HuntingCube; Itanagar; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

HuntingCube in India is seeking a Senior/Lead RTL Design Engineer to drive advanced RTL/ASIC design efforts in Semiconductor/VLSI. The role targets 8–12 years of hands-on experience in Verilog/SystemVerilog and leadership in complex clocking and interface blocks.

The candidate will work on high-speed interfaces, memory controllers, and SOC interconnects, delivering robust RTL solutions and robust debugging capabilities across PCIe and DDR/X interfaces.

Qualifications

• 8–12 years of RTL design experience in semiconductor/ASIC domains.
• Strong Verilog and SystemVerilog coding and debugging proficiency.
• Expertise in clock design and clock-domain crossing, timing constraints, and synthesis.
• Experience with PCIe, memory controllers, and high-speed interfaces.

Skills

Verilog

SystemVerilog

RTL debugging

Clock design

Clock-domain crossing

FIFOs

State machines

Pipelining

PCIe controllers

Ethernet MACs

DDR controllers

Memory subsystems

Job description

Job Description:

Role Overview

Senior / Lead RTL Design Engineer - Semiconductor / VLSI / ASIC Design Senior / Lead RTL Design Engineer Experience: 8–12 Years Domain: Semiconductor / VLSI / ASIC Design

Key Skills

• Verilog
• SystemVerilog
• RTL debugging
• Clock and reset design
• Clock-domain crossing techniques
• FIFOs and asynchronous interfaces
• State machines and control logic
• Pipelining
• Bus/interconnect protocols
• Lint
• CDC/RDC
• SDC/timing constraints
• Synthesis
• Static timing analysis
• PCI Express (PCIe) controllers/subsystems
• Ethernet controllers/MACs
• DDR/LPDDR controllers
• DMA engines
• AXI/AHB/APB interfaces and SoC interconnects
• High-speed interface controller logic
• Memory controllers or memory subsystems

Required Skills

['Verilog', 'SystemVerilog', 'RTL debugging', 'Clock and reset design', 'Clock-domain crossing techniques', 'FIFOs and asynchronous interfaces', 'State machines and control logic', 'Pipelining', 'Bus/interconnect protocols', 'Lint', 'CDC/RDC', 'SDC/timing constraints', 'Synthesis', 'Static timing analysis']

Additional Information

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