Senior OR Lead RTL Design Engineer

Zyoin Group; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Zyoin Group's client, a signal processing infrastructure company, seeks a strong RTL expert to lead the silicon program to tapeout and to build and lead an RTL team of 5–7 engineers.

You will write and review SystemVerilog, own the synthesis flow (Design Compiler or Genus) and timing closure, define SDC constraints, and coordinate with the outsource partner on GDSII handover, while collaborating with verification to reach coverage closure.

Qualifications

• 4+ years RTL design experience in SystemVerilog.
• At least 1 tapeout through to GDSII.
• Synthesis and timing closure experience with Design Compiler or Genus.
• Strong code review and hands-on leadership skills.

Responsibilities

• Translate the architecture spec into synthesizable SystemVerilog.
• Own RTL coding standards, linting rules, and design methodology.
• Lead a team of 5-7 RTL engineers through the full design cycle.
• Own the synthesis flow and drive timing closure.
• Define and maintain SDC timing constraints.
• Review all RTL submissions for correctness and synthesizability.
• Coordinate with outsource partner on GDSII handover (netlist, constraints, floorplan).
• Collaborate with verification to resolve bugs and achieve coverage closure.

Skills

SystemVerilog

RTL design

Synthesis

Timing closure

Code review

Team leadership

Tools

Design Compiler

Genus

PrimeTime

Tempus

Job description

Our Client is a signal processing infrastructure company. they build the full acquisition and compute stack for human-aware technology - from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical workloads.

Our Client's Silicon is their ground-up effort to build a new compute category.

About the Role

We need a strong RTL expert who can lead our silicon program to tapeout. You will be the technical bridge between our architecture and our design partner, owning every step from RTL freeze to GDSII handoff, working with our partners. You will also build and lead the RTL team of 5-7 engineers. This is a hands-on lead role. You write RTL, review RTL, run synthesis, and own the result. The architect defines what gets built. You own how it gets built.

Responsibilities

• Translate the architecture specification into synthesizable SystemVerilog


• Own the RTL coding standards, linting rules, and design methodology


• Lead a team of 5-7 RTL engineers through the full design cycle


• Own the synthesis flow (Design Compiler or Genus) and drive timing closure


• Define and maintain SDC timing constraints


• Review all RTL code submissions for correctness, synthesizability, and style


• Coordinate with the outsource partner on GDSII handover (netlist, constraints, floorplan


• guidance)


• Work closely with the verification team to resolve bugs and achieve coverage closure

Requirements

Experience

• 4+ OR 7+ years of RTL design experience in SystemVerilog


• At least 1 tapeout through to GDSII (not just RTL - you've seen the full flow)


• Synthesis and timing closure experience (Design Compiler or Genus, PrimeTime or


• Tempus)


• Processor, DSP, or datapath-heavy design experience


• Familiarity with advanced process nodes (28nm class or below)


• Strong code review skills, you can spot timing hazards, FSM issues, and non-synthesizable patterns in review


• Comfortable leading a small team while remaining hands-on

Good to have

• Experience with deterministic/real-time architectures (no caches, fixed latencies)


• Formal verification awareness (writing SVA, working with formal tools)