Senior RTL Design Engineer

ACL Digital; Bengaluru; On-site; INR 2,500,000 - 4,000,000; Full time

Job summary

ACL Digital in Bengaluru is seeking an experienced RTL Design engineer with 5+ years of work in low-power RTL, microarchitecture and timing closure. Proficiency in Verilog and ASIC tools like VCS, Verdi, and Design Compiler is required. Knowledge of power estimation tools and scripting (Shell, Python) is a plus.

Prior DSP/AI or DRAM controller exposure is advantageous. Candidate will work on RTL optimization for area and power, explore hardware architectures, and may contribute to ML/AI related

Qualifications

• 5+ years in RTL design with low-power focus.
• Experience with ASIC tools including VCS, Verdi, Design Compiler.
• Knowledge of power estimation tools and scripting languages.

Skills

Low power RTL design

Microarchitecture

Synthesis

Timing closure

Verilog

Power estimation

Area optimization

Machine learning/AI domain (plus)

DRAM memory controllers (plus)

Lint

CDC

RTL Design for PCIe/CXL

Tools

VCS

Verdi

Design Compiler

Spyglass

PTPX

Shell scripting

Perl

Python

C language

Job description

Hi All,

Job Location: Bangalore

Notice Period: 15 days to 30 Days

Minimum: 5+ Years

• 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.
• 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus.
• 3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus.
• 4. Experience with hardware architecture exploration, performance modelling will be a big plus.
• 5. Prior experience in Machine learning/Artificial Intelligence domain and/or DRAM Memory controllers is a plus.
• 6.Must have experience in Lint and CDC.
• 7.Must have RTL Design worked on PCIe/CXL

Thanks,

K Himabindu