Senior Principal Verification Engineer

Mulya Technologies; Bengaluru; Hybrid; INR 3,000,000 - 4,800,000; Full time

Job summary

Mulya Technologies in Bengaluru is seeking an experienced SPE Verification Engineer to join the Memory Controller IP team, focusing on pre-silicon RTL verification for DDR/HBM/GDDR/LPDDR DRAM controllers. The role is full-time with a hybrid onsite arrangement in India.

You will develop testbenches, plan functional coverage, and drive regression tests across advanced memory controller technologies, reporting to an onsite manager in India Memory Controller Verification.

Qualifications

• Bachelor's Degree in EE/CS required.
• SystemVerilog testbench and RTL fluency (Verilog/SystemVerilog) a must.
• Pre-existing familiarity with DDR DRAM technology is preferred.
• Python and TCL scripting experience is preferred.

Responsibilities

• Testbench and test sequence development for verification of new controller technologies and features
• Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
• Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design
• Development & support of Verification environment scripting and capabilities

Skills

SystemVerilog

RTL verification

Functional coverage

Education

Bachelor's Degree in EE/CS

Tools

Verilog

Python

TCL scripting

Job description

Large Semicon MNC With Market Cap ove 10 Billion USD

Overview:

We are a premier chip and silicon IP provider, is seeking to hire an exceptional SPE Verification Engineer to join our Memory Controller IP team in Bangalore, India. The successful candidate will participate in pre-silicon RTL Verification activities related to Memory Controller SoftIP development, on leading-edge DDR, HBM, GDDR, and LPDDR DRAM controller technologies. This is a Full Time position, reporting to a local onsite manager of India Memory Controller Verification.

We offer a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite while also allowing for two days of remote work.

Responsibilities:

Duties in this position will include:

• Testbench and test sequence development for verification of new controller technologies and features
• Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
• Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design
• Development & support of Verification environment scripting and capabilities

Qualifications:

Bachelors Degree or above in EE/CS, minimum 12+ years experience with HDL logic Design-Verification

• System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must
• Pre-existing Experience / familiarity with DDR DRAM technology a strong preference
• Working experience with Python and TCL scripting languages preferred