Senior Design Verification Engineer - Memory Controller

UST; Bengaluru; On-site; INR 1,000,000 - 1,200,000; Full time

Job summary

UST is seeking a Senior Design Verification Engineer - Memory Controller to work on DRAM Memory Controller functional units. This role involves verifying designs for compliance with protocols such as LPDDR4/5 and DDR4/5 through rigorous testing.

The ideal candidate will possess expertise in developing verification plans, performing power-aware simulations, and debugging RTL models. Strong understanding of memory controller microarchitecture is required. Interested candidates should share their resumes with [e-mail].

Qualifications

• Experience with DRAM protocols (LPDDR4/5, DDR4/5, HBM) is essential.
• Strong understanding of memory controller microarchitecture required.
• Ability to perform power-aware simulations and coverage analysis.

Responsibilities

• Verify designs for DRAM protocol compliance and functionality.
• Develop and execute design verification plans.
• Perform power-aware simulations and design compliance checks.
• Maintain reusable verification environments and perform debugging.

Skills

DRAM protocol compliance

Functional verification

Low-power design

UVM methodologies

Debugging RTL models

Tools

Simulation tools

Testbenches

Job description

Position: Senior Design Verification Engineer - Memory Controller

Job Overview

As a Senior Design Verification Engineer - Memory Controller, you would responsible for one or more functional units of the DRAM Memory Controller while working closely with architecture and design teams to meet all functional and performance requirements.

Responsibilities

• Verify designs for DRAM (e.g., LPDDR4/5, DDR4/5, HBM) protocol compliance and functionality through rigorous testing and simulation.
• Develop and execute design verification plans to ensure functional correctness and compliance with specifications.
• Perform power-aware simulations and ensure low-power design compliance using UPF (Unified Power Format) standards.
• Develop and maintain reusable verification environments, including testbenches and test cases, using industry-standard methodologies (e.g., UVM).
• Debug functional errors in the RTL model using simulation and debug tools with an in-depth understanding of the DRAM protocol and memory controller microarchitecture.
• Define and implement functional coverage.
• Perform coverage analysis and identify testing gaps.

Please share your resume to [e-mail]