DFT Engineer

Erbity; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Erbity is seeking a Senior DFT (Design-for-Test) Engineer to architect and validate test methodologies in complex SoC/ASIC designs. The role requires deep technical expertise in scan insertion, ATPG, and MBIST, alongside collaboration with RTL, verification, and physical design teams. Ideal candidates will have 5-8 years in DFT, experience in debugging silicon test issues, and scripting capabilities in Python, Perl, or TCL. This position is crucial for ensuring manufacturability and efficient silicon bring-up.

Qualifications

• Typically 5-8 years in DFT for complex SoCs/ASICs.
• Experienced in scan insertion, ATPG, MBIST, boundary scan, JTAG.
• Experience in debugging silicon test issues and yield analysis.

Responsibilities

• Define and implement DFT methodologies for SoCs and test chips.
• Generate ATPG patterns for various fault types.
• Debug test pattern issues during silicon bring-up.

Skills

DFT methodologies

Scan insertion

ATPG

Debugging silicon test issues

Scripting (Python, Perl, TCL)

Education

Bachelor's/master's in electrical engineering, Microelectronics, or related field

Job description

A Senior DFT (Design-for-Test) Engineer is responsible for architecting, implementing, and validating test methodologies in complex SoC/ASIC designs, ensuring manufacturability, reliability, and efficient silicon bring-up. The role blends deep technical expertise in scan insertion, ATPG, MBIST, and test pattern validation with cross‑functional collaboration across RTL, verification, and physical design teams.

DFT Architecture & Implementation

• Define and implement DFT methodologies for SoCs, MCUs, or test chips
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level
• Architect innovative DFT techniques for advanced process nodes.

Test Pattern Development & Validation

• Generate ATPG patterns for stuck‑at, transition, and path delay faults
• Debug test pattern issues during silicon bring‑up
• Ensure highest stability and coverage of test patterns on ATE (Automatic Test Equipment).

Cross‑Functional Collaboration

• Work closely with RTL design, verification, physical implementation, and test engineering teams
• Support silicon characterization and yield improvement activities
• Contribute to overall microcontroller or SoC DFT methodology
• Bachelor's/master's in electrical engineering, Microelectronics, or related field

Requirements

• Typically 5‑8 years in DFT for complex SoCs/ASICs
• Experienced in scan insertion, ATPG, MBIST, boundary scan, JTAG
• Debugging silicon test issues and yield analysis
• Experience in scripting and programming using Python, Perl, TCL