DFT Engineer

Erbity; Chennai District; On-site; INR 1,000,000 - 1,800,000; Full time

Job summary

Erbity is seeking a Senior DFT Engineer to architect and implement test methodologies for complex SoCs/ASICs, ensuring manufacturability and reliable silicon bring-up. You will work across RTL, verification, and physical design teams to define scalable DFT strategies.

Key activities include inserting scan chains, boundary scan, MBIST, and repair logic; developing ATPG patterns for stuck-at and path faults; debugging test issues; and driving yield improvement through tooling and characterization

Qualifications

• 5–8 years of DFT experience in complex SoCs/ASICs.
• Experience with scan insertion, ATPG, MBIST, boundary scan, and JTAG.
• Ability to debug silicon test issues and analyze yield.

Responsibilities

• Define and implement DFT methodologies for SoCs, MCUs, or test chips.
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level.
• Architect innovative DFT techniques for advanced process nodes.
• Generate ATPG patterns for stuck-at, transition, and path delay faults.
• Debug test pattern issues during silicon bring-up.
• Ensure high stability and coverage of test patterns on ATE.
• Collaborate with RTL design, verification, and physical design teams.
• Support silicon characterization and yield improvement activities.
• Contribute to overall microcontroller or SoC DFT methodology.

Skills

Scan insertion

ATPG

MBIST

Boundary scan

JTAG

Scripting languages

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

Tools

Python

Perl

TCL

Job description

A Senior DFT (Design-for-Test) Engineer is responsible for architecting, implementing, and validating test methodologies in complex SoC/ASIC designs, ensuring manufacturability, reliability, and efficient silicon bring-up. The role blends deep technical expertise in scan insertion, ATPG, MBIST, and test pattern validation with cross-functional collaboration across RTL, verification, and physical design teams.

DFT Architecture & Implementation

• Define and implement DFT methodologies for SoCs, MCUs, or test chips
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level
• Architect innovative DFT techniques for advanced process nodes.

Test Pattern Development & Validation

• Generate ATPG patterns for stuck-at, transition, and path delay faults
• Debug test pattern issues during silicon bring-up
• Ensure highest stability and coverage of test patterns on ATE (Automatic Test Equipment).

Cross-Functional Collaboration

• Work closely with RTL design, verification, physical implementation, and test engineering teams
• Support silicon characterization and yield improvement activities
• Contribute to overall microcontroller or SoC DFT methodology
• Bachelor's/master's in electrical engineering, Microelectronics, or related field

Requirements

• Typically, 5-8 years in DFT for complex SoCs/ASICs
• Experienced in Scan insertion, ATPG, MBIST, boundary scan, JTAG
• Debugging silicon test issues and yield analysis
• Experience in Scripting/ programming using Python, Perl, TCL