DFT Engineer

Erbity; Dadri; On-site; INR 1,800,000 - 2,800,000; Full time

Job summary

Erbity in India is seeking a Senior DFT Engineer to design, implement, and validate test methodologies for complex SoCs/ASICs, ensuring manufacturability and reliable silicon bring-up.

The role covers scan insertion, ATPG, MBIST, boundary scan, and cross-functional collaboration with RTL, verification, and physical design teams; requires 5–8 years of DFT experience and scripting skills in Python, Perl, or TCL.

Qualifications

• 5-8 years of experience in DFT for complex SoCs/ASICs.
• Experience in scan insertion, ATPG, MBIST, boundary scan, JTAG.
• Debugging silicon test issues and yield analysis.
• Proficiency in scripting languages: Python, Perl, TCL.

Responsibilities

• Define and implement DFT methodologies for SoCs, MCUs, or test chips.
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level.
• Architect innovative DFT techniques for advanced process nodes.
• Generate ATPG patterns for stuck-at, transition, and path delay faults.
• Debug test pattern issues during silicon bring-up.
• Ensure stability and coverage of test patterns on ATE.
• Work with RTL design, verification, physical implementation, and test engineering teams.
• Support silicon characterization and yield improvement activities.
• Contribute to overall microcontroller or SoC DFT methodology.

Skills

DFT

ATPG

MBIST

Scan Insertion

Test Patterns

Yield Analysis

Silicon Bring-up

Education

Bachelor's/Master's in Electrical Engineering or Microelectronics

Tools

Python

Perl

TCL

JTAG

Boundary Scan

Job description

A Senior DFT (Design-for-Test) Engineer is responsible for architecting, implementing, and validating test methodologies in complex SoC/ASIC designs, ensuring manufacturability, reliability, and efficient silicon bring-up. The role blends deep technical expertise in scan insertion, ATPG, MBIST, and test pattern validation with cross-functional collaboration across RTL, verification, and physical design teams.

DFT Architecture & Implementation

• Define and implement DFT methodologies for SoCs, MCUs, or test chips
• Insert scan chains, boundary scan, MBIST, and repair logic at RTL/gate level
• Architect innovative DFT techniques for advanced process nodes.

Test Pattern Development & Validation

• Generate ATPG patterns for stuck-at, transition, and path delay faults
• Debug test pattern issues during silicon bring-up
• Ensure highest stability and coverage of test patterns on ATE (Automatic Test Equipment).

Cross-Functional Collaboration

• Work closely with RTL design, verification, physical implementation, and test engineering teams
• Support silicon characterization and yield improvement activities
• Contribute to overall microcontroller or SoC DFT methodology
• Bachelor's/master's in electrical engineering, Microelectronics, or related field

Requirements

• Typically, 5-8 years in DFT for complex SoCs/ASICs
• Experienced in Scan insertion, ATPG, MBIST, boundary scan, JTAG
• Debugging silicon test issues and yield analysis
• Experience in Scripting/ programming using Python, Perl, TCL