Senior Physical Design Engineer - Pune

N Human Resources & Management Systems; Pune District; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

N Human Resources & Management Systems is seeking a Senior Physical Design Engineer to own full-chip and block-level PnR flows, drive timing/power/signoff closure, and collaborate with cross-functional design teams on advanced-node tapeouts.

Responsibilities include leading floorplanning, placement, CTS, routing, and physical design using ICC2/Innovus, plus driving STA and signoffs while resolving timing and power closure issues.

Qualifications

• 4+ years of hands-on Physical Design experience across Synthesis-to-GDSII.
• Strong command of ICC2/Innovus.
• Experience taking multiple chips to tapeout on advanced nodes.
• Solid understanding of STA, power and signal-integrity closure.

Responsibilities

• Lead floorplanning, placement, CTS, routing and physical design implementation using Synopsys ICC2/Cadence Innovus.
• Drive STA, IR-drop/EM, and physical verification signoff.
• Resolve timing, congestion and power closure issues.
• Collaborate with CAD, methodology and IP teams on delivery cadence.

Skills

Senior PD Engineer

Floorplanning

Timing closure

Education

Bachelor's/Master's in EE/ECE

Tools

ICC2/Innovus

Job description

N Human Resources & Management Systems | Full time

We are looking for a Senior Physical Design Engineer to join our VLSI delivery team. You will own full-chip and block-level PnR flows, drive timing/power/signoff closure, and collaborate with cross-functional design teams on advanced-node tapeouts.

Key Responsibilities:

• Lead floorplanning, placement, CTS, routing and physical design implementation using Synopsys ICC2/Cadence Innovus
• Drive STA, IR-drop/EM, and physical verification signoff
• Resolve timing, congestion and power closure issues
• Collaborate with CAD, methodology and IP teams on delivery cadence

Requirements:

• 4+ years of hands-on Physical Design experience across Synthesis-to-GDSII
• Strong command of ICC2/Innovus
• Experience taking multiple chips to tapeout on advanced nodes
• Solid understanding of STA, power and signal-integrity closure
• Bachelor's/Master's in EE/ECE or related field