Senior Physical Design Engineer - Chennai

N Human Resources & Management Systems; Chennai District; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

N Human Resources & Management Systems in Chennai is seeking a Senior Physical Design Engineer to own full-chip and block-level PnR flows, drive timing/power/signoff closure, and collaborate with cross-functional design teams on advanced-node tapeouts.

The role requires 4+ years in Physical Design, strong ICC2/Innovus expertise, and a solid background in STA, power integrity, and timing closure. Bachelor’s/Master’s in EE/ECE is preferred for this on-site position in Chennai.

Qualifications

• 4+ years of hands-on Physical Design experience from Synthesis to GDSII.
• Proficiency with ICC2 and Innovus.
• Experience taping out multiple chips on advanced nodes.
• Strong understanding of STA, power and signal-integrity closure.
• Bachelor’s or Master’s degree in EE/ECE or a related field.

Responsibilities

• Lead floorplanning, placement, CTS, routing and physical design implementation using Synopsys ICC2/Cadence Innovus.
• Drive STA, IR-drop/EM, and physical verification signoff.
• Resolve timing, congestion and power closure issues.
• Collaborate with CAD, methodology and IP teams on delivery cadence.

Skills

Physical Design

ICC2

Innovus

Timing closure

Power integrity

Education

Bachelor’s/Master’s in EE/ECE or related field

Job description

N Human Resources & Management Systems | Full time

Senior Physical Design Engineer - Chennai

We are looking for a Senior Physical Design Engineer to join our VLSI delivery team. You will own full-chip and block-level PnR flows, drive timing/power/signoff closure, and collaborate with cross-functional design teams on advanced-node tapeouts.

Key Responsibilities:

• - Lead floorplanning, placement, CTS, routing and physical design implementation using Synopsys ICC2/Cadence Innovus
• - Drive STA, IR-drop/EM, and physical verification signoff
• - Resolve timing, congestion and power closure issues
• - Collaborate with CAD, methodology and IP teams on delivery cadence

Requirements:

• - 4+ years of hands-on Physical Design experience across Synthesis-to-GDSII
• - Strong command of ICC2/Innovus
• - Experience taking multiple chips to tapeout on advanced nodes
• - Solid understanding of STA, power and signal-integrity closure
• - Bachelor's/Master's in EE/ECE or related field