Senior Physical Design Engineer - Coimbatore

N Human Resources & Management Systems; Coimbatore District; On-site; INR 1,200,000 - 2,400,000; Full time

Job summary

N Human Resources & Management Systems in Coimbatore is seeking a Senior Physical Design Engineer to drive full-chip and block-level PnR flows, and collaborate with cross-functional teams on advanced-node tapeouts.

The role focuses on timing, power, and signoff closure, with hands-on leadership across floorplanning, placement, CTS, routing, and physical verification in a dynamic VLSI delivery team.

Qualifications

• 4+ years hands-on physical design experience from Synthesis to GDSII.
• Strong command of ICC2/Innovus.
• Experience taking multiple chips to tapeout on advanced nodes.

Responsibilities

• Lead floorplanning, placement, CTS, routing and physical design implementation.
• Drive STA, IR-drop/EM and physical verification signoff.
• Resolve timing, congestion and power closure issues.
• Collaborate with CAD, methodology and IP teams on delivery cadence.

Skills

Physical design

Timing/power/signoff

Cross-functional collaboration

Education

Bachelor's/Master's in EE/ECE

Tools

ICC2

Innovus

Job description

N Human Resources & Management Systems | Full time

Senior Physical Design Engineer - Coimbatore

Coimbatore, India | Posted on 09/14/2026

We are looking for a Senior Physical Design Engineer to join our VLSI delivery team. You will own full-chip and block-level PnR flows, drive timing/power/signoff closure, and collaborate with cross-functional design teams on advanced-node tapeouts.

Key Responsibilities:

• Lead floorplanning, placement, CTS, routing and physical design implementation using Synopsys ICC2/Cadence Innovus
• Drive STA, IR-drop/EM, and physical verification signoff
• Resolve timing, congestion and power closure issues
• Collaborate with CAD, methodology and IP teams on delivery cadence

Requirements:

• 4+ years of hands-on Physical Design experience across Synthesis-to-GDSII
• Strong command of ICC2/Innovus
• Experience taking multiple chips to tapeout on advanced nodes
• Solid understanding of STA, power and signal-integrity closure
• Bachelor's/Master's in EE/ECE or related field