Senior Asic Engineer

Acesoft Labs; Hyderabad; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Acesoft Labs in Hyderabad, India, seeks highly experienced Senior ASIC Engineers to lead and contribute to complex ASIC projects across advanced nodes.

You will own physical design and verification, drive tapeouts, and mentor junior engineers, with hands-on use of Cadence Innovus/Tempus and Mentor Caliber.

Candidates should have 5+ years in physical design and verification, fluency with high-speed protocols, and a track record of successful tapeouts.

Qualifications

• Extensive experience in physical design and verification.
• Expertise in advanced UVM verification methodologies.
• Strong understanding of high-speed protocols.
• Proven track record of successful tapeouts.
• Proficiency in Cadence and Mentor tools.

Responsibilities

• Lead physical design implementations including floorplanning, placement, routing, and RC extraction.
• Develop and implement advanced UVM verification environments for IP and full-chip verification.
• Verify high-speed protocols such as SERDES, PCIe, UFS, DDR.
• Manage tapeout activities across multiple tapeouts.
• Coordinate with global teams on project planning and risk management.
• Mentor junior engineers and document processes.

Skills

Physical design

ASIC verification

UVM verification

High-speed protocols

Leadership

Project planning

Communication

Tools

Innovus

Tempus

Mentor Caliber

Job description

We are looking for highly experienced Senior ASIC Engineers to lead and contribute to complex ASIC projects. This role requires expertise in advanced physical design, verification, and tapeout processes. The ideal candidate will have a proven track record of delivering high-quality ASIC designs in advanced technology nodes.

Responsibilities:

Lead and execute complex physical design implementations, including block-level low power aware floorplanning, placement, CTS, routing, RC extraction, STA, IR/EM analysis, and DRC/LVS/ERC.

Manage hierarchical physical verification and signoff closures.

Develop and implement advanced UVM verification environments for IP and full-chip verification.

Verify complex high-speed protocols (SERDES, UNIPRO, PCIE, UFS, DDR).

Drive STA closure at block and chip levels.

Manage and contribute to tapeout activities, with experience in multiple tapeouts.

Work with advanced process technology nodes (7nm, 6nm, 5nm).

Utilize Cadence (Innovus, Tempus) and Mentor Caliber tools effectively.

Guide and mentor junior engineers.

Collaborate with global teams to ensure project success.

Contribute to project planning, scheduling, and risk management.

Develop and maintain comprehensive documentation.

Required Skills:

Extensive experience in physical design and verification.

Expertise in advanced UVM verification methodologies.

Strong understanding of high-speed protocols.

Proven track record of successful tapeouts.

Proficiency in Cadence and Mentor tools.

Strong analytical and problem-solving skills.

Excellent communication and leadership skills.

Experience with advanced process technology nodes.

Knowledge of digital electronics and microprocessors.

Experience:

5+ years of relevant experience, with a preference for 7+ years.