Senior Physical Design Engineer

L&T Semiconductor Technologies; Bengaluru; On-site; INR 1,500,000 - 2,800,000; Full time

Job summary

L&T Semiconductor Technologies in Bengaluru seeks a Senior SoC Physical Design Implementation Engineer responsible for RTL2GDS with aligned PPA and sign-off per PDK requirements.

Lead PD for Top/SS/Partitions, mentor teams, and coordinate with RTL, verification, and post-silicon groups to ensure seamless sign-off; drive flow adoption and tool efficacy.

This role emphasizes quality, compliance, and ongoing process improvement.

Qualifications

• 6+ years in physical design with sign-off exposure.
• Hands-on experience with RTL2GDS flows and PNR/DRC/LVS sign-off.
• Strong leadership and mentoring skills to guide design teams.

Responsibilities

• Lead Physical Design of Top/SS/Partitions and align with project objectives.
• Mentor and develop team members, fostering excellence, collaboration and continuous learning.
• Coordinate cross-functional teams including RTL designers, verification engineers, and post-silicon teams to ensure seamless sign-off processes.
• Develop and implement strategies to ensure quality and reliability of physical designs.
• Establish methodologies, checklists for BE Integration/PNR/Floor Plan/Power Mesh/Clocking/Power integrity and timing sign-off, DRC/LVS clean-up.
• Adopt latest tools and methodologies to improve sign-off efficiency.
• Provide expert guidance on sign-off issues related to PNR and timing/physical verification.
• Collaborate with design and verification teams to ensure sign-off readiness.
• Collaborate with EDA tool vendors to meet tool feature needs and support.
• Evaluate and recommend new tools and methodologies for physical design and sign-off.
• Ensure quality standards before sign-off including timing, power, and physical integrity.

Skills

Leadership

Team mentoring

Cross-functional collaboration

Sign-off analysis

Problem solving

Tools

EDA tools

Job description

As a Senior SoC Physical Design Implementation, the role includes working on the SoC/Subsystem level RTL2GDS Implementation with aligned PPA & Power/DRC Signoff as per PDK requirements. The role also oversee the Implementation strategy with Signoff Analysis, Timing/LV/EM/IR Analysis/ESD Analysis with driving methodology and commanding tools with flow. Collaboration as partner with Frontend and Packaging Teams/Full Chip Integration Teams. This position involves technical expertise and problem-solving skills to manage the estimation and project effectively.

Experience: 6 to 11 years

Responsibilities:

• Leadership:
• Manage the Physical Design of Top/SS/Partitions, ensuring alignment with the overall project and company objectives.
• Mentor and develop team members, fostering a culture of excellence, collaboration, and continuous learning.
• Coordinate cross-functional teams including RTL designers, verification engineers, and post-silicon teams to ensure seamless sign-off processes.

2 Physical Design Integration & Implementation:

• Develop and implementation strategies that ensure the quality and reliability of physical designs.
• Establish and enforce methodologies, best practices, and checklists for BE Integration/PNR/Floor Plan/Power Mesh/Clocking/Power integrity, Signal Integrity, Timing Signoff DRC/LVS clean-up, and other sign-off criteria.
• Adoption of the latest tools, technologies, and methodologies to improve sign-off efficiency and effectiveness.

3 Technical Oversight:

• Provide expert guidance in resolving complex sign-off issues related to PNR, and timing/physical verification.
• Analyze and resolve any bottlenecks in the physical design process, ensuring design meets all performance, area, and power requirements.
• Collaborate closely with the design and verification teams to ensure that the physical design is sign-off ready.
• Collaboration with EDA:
• Collaborate EDA tool vendors, ensuring the company’s needs are met about tool features, enhancements, and support.
• Evaluate and recommend new tools and methodologies for physical design and sign-off.

5 Quality:

• Ensure that all designs meet the required quality standards before sign-off, including thorough verification of timing, power, and physical integrity. Implement robust quality control measures to ensure zero-defect silicon and first-time-right success.

6 Compliance and Standards:

• Ensure compliance with industry standards and regulatory requirements during the sign-off process.