Physical Design (PD) Lead

Cyient; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Cyient in India seeks a Senior Principal Engineer to lead semiconductor design across architecture, RTL, and physical implementation. You will own the complete physical design flow from synthesis handoff to tapeout readiness, driving design closure and signoff with cross-functional teams.

The role requires hands-on FinFET experience (16nm/12nm/7nm; 5nm preferred) and deep expertise in Synopsys ICC2, Fusion Compiler, PrimeTime, and signoff tools.

Qualifications

• Hands-on experience in physical design from synthesis to tapeout.
• Experience with 16nm/12nm/7nm FinFETs; 5nm preferred.
• Proficiency with Synopsys tool suite and signoff flow.

Responsibilities

• Own complete Physical Design flow from synthesis handoff to GDSII tapeout.
• Drive floorplanning, power planning, placement, CTS, routing and optimization.
• Lead timing closure and ECO implementation for multiple corners.
• Perform DRC/LVS/ERC signoff checks and SI/PI analysis.
• Collaborate with RTL, DFT, STA, and P&R teams to ensure convergence.

Skills

Floorplanning

Power planning

Placement optimization

Clock Tree Synthesis

Routing optimization

Timing closure

ECO closure

Signoff closure

Low power implementation

Design for Manufacturability

Tools

Synopsys ICC2

Fusion Compiler

PrimeTime

StarRC

IC Validator

Design Compiler

Job description

Physical Design with Synopsys Tool Exp:

Key Responsibilities

Physical Design Implementation

• Own complete Physical Design flow from synthesis handoff to GDSII.
• Perform Floor planning, Power Planning, Placement, CTS, Routing, Physical Optimization, and ECO implementation.
• Drive block-level and full-chip design closure on advanced FinFET nodes.
• Execute congestion analysis and optimization to achieve PPA targets.

Timing Closure

• Perform timing analysis using Synopsys PrimeTime.
• Resolve setup, hold, transition, capacitance, and noise violations.
• Drive MCMM timing closure across multiple corners and modes.
• Implement timing ECOs and optimize critical timing paths.

Physical Verification & Signoff

• Run and debug DRC/LVS/ERC violations using industry-standard signoff tools.
• Analyze and resolve physical design issues impacting manufacturability.
• Ensure successful tapeout readiness.

Power & Signal Integrity

• Perform IR Drop and EM analysis.
• Optimize power distribution networks.
• Perform signal integrity checks and noise analysis to ensure robust silicon performance.

Design Optimization

• Drive area, power, and performance optimization.
• Work closely with RTL, DFT, STA, and P&R teams to achieve design convergence.
• Support Design-for-Manufacturability (DFM) requirements.

Required Technical Skills

Synopsys Tool Expertise

• Strong expertise in:
  • Synopsys ICC2
  • Fusion Compiler
  • PrimeTime
  • StarRC
  • IC Validator
  • Design Compiler (Good to Have)

Physical Design Skills

• Floorplanning
• Power Planning
• Placement Optimization
• Clock Tree Synthesis (CTS)
• Routing & Optimization
• Timing Closure
• ECO Closure
• Signoff Closure
• Low Power Implementation

FinFET Experience

• Mandatory hands-on experience in:
  • 16nm FinFET
  • 12nm FinFET
  • 7nm FinFET
  • 5nm FinFET (Preferred)

Signoff Expertise

• MCMM Timing Closure
• Signal Integrity Analysis
• Crosstalk Analysis
• IR Drop Analysis
• EM Analysis
• DRC/LVS Closure

Roles and Responsibilities

A seasoned technical leader with deep expertise in semiconductor design and development, the Senior Principal Engineer plays a pivotal role in driving innovation across all phases of chip development - from architecture and RTL design to physical implementation, verification, and silicon validation. This role is responsible for setting technical direction on cutting-edge projects, influencing product roadmaps, and ensuring the successful delivery of high-performance, low-power, and cost-effective integrated circuits. Acting as a mentor and technical advisor, the Senior Principal Engineer collaborates with cross-functional teams across architecture, design, verification, DFT, and packaging to push the boundaries of silicon technology while aligning engineering execution with business and product strategies.