Senior Lead Engineer - STA

NXP Semiconductors; Dadri; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

NXP Semiconductors in India seeks a Digital Physical Design Engineer responsible for complete STA signoff for the SOC or Subsystem. You will write timing constraints and interact with Frontend, DFT and IP to ensure correct constraints, refining them throughout the design cycle and validating them against SOC constraints.

Candidate must lead signoff activities, generate/validate SDF, and ensure SI closure. Exposure to advanced nodes (16nm, 5nm) and familiarity with physical design flows

Qualifications

• Experience writing and validating timing constraints for SOC/subsystem designs.
• Strong understanding of STA signoff flow and signoff ownership.
• Exposure to AI techniques applied to timing analysis.
• Experience generating and validating SDF for timing verification.
• Knowledge of physical design flows: placement, CTS, routing.

Responsibilities

• Write timing constraints and drive constraints validation across SOC design.
• Collaborate with Frontend, DFT, and IP teams to ensure constraints correctness.
• Lead timing signoff through tapeout readiness for subsystem or full chip.
• Contribute to SI closure and encode best PD strategies for technology nodes.

Skills

STA signoff

Timing constraints

AI in STA

SDF generation

Physical design knowledge

Placement & Routing

SI closure

Job description

The Digital Physical Design Engineer is responsible for complete STA signoff for the SOC or Subsystem.

The individual is responsible for writing timing constraints, interacting with the counterpart functions, such as Frontend, DFT and IP to write correct constraints, refining constraints throughout SOC design cycle and constraints validation.

The individual must have exposure of AI and use AI in STA activities.

The individual is responsible for complete timing signoff till the tapeout for subsystem or full chip.

Must have leading capabilities on signoff function.

Must have worked on SDF generation and validation.

Must have all knowledge of SI closure.

Must have exposure to higher tech nodes such as 16nm and 5nm.

Must be conversant with physical design flows and functions and must possess good knowledge of placement, CTS and Routing.

The individual contributes to problem solving related to physical design. Contributes to define best Physical design strategy per technology node.

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